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DS110DF111: DS110DF111 couldn't link with SFI interface with EEPROM mode

Part Number: DS110DF111
Other Parts Discussed in Thread: USB2ANY

Hello,

Our customer used EEPROM mode to configure DS110DF111SQ, it couldn't link of SFI interface. But when configured with PIN control mode, it could link normally. 

 1.PIN control  mode, normally link. 

VOD Setting:VODA/B=0(600mv)

De-Emphasis Setting:DEMA/B=0(0db)

2. EEPROM mode, SFI interface couldn't link. The registers are as following:

 REG 00x2F[7:4]=1100;//10.3125 Gbps data rate。

 REG 0x31[6:5]=00; //Adapt mode 0。

 REG 0x2D[3]=1;//override the EQ setting。

 REG 0x03[7:0]=00; //EQ=0。

 REG 0X3A[7:0]=00; 

 REG 0x40[7:0]=00; 

 REG 0x1E[3]=1;//Disable the DFE。

 REG 0x2d[2:0]=000;//Driver VOD 600mv。

 REG 0x15[2:0]=000;//De-Emphasis 0db。

 REG 0x09[5]=1;//Enable Override Output Mux。

 REG 0x1E[7:5]=000; //Select RAW data (CDR Bypass)。

In addition, when using EEPROM mode, do we need DPS-DONGLE-EVM or USB2ANY tool? Or DPS-DONGLE-EVM or USB2ANY need only  in SMbus  slave mode? But without  DPS-DONGLE-EVM or USB2ANY tool, the high level page couldn't  detect the status  of  SigCon Architect .Please refer to the below screen of high level page.

Our customer used SigCon Architect to generate the HEX file and downloaded it into EEPROM, and then he tested LOS and lock pin are always low level.  Could you please help to analyze? 

Best regards

kailyn

  • Please provide the following:

    • Retimer EEPROM HEX file being used by customer
    • A schematic showing how the retimer pins are configured, including EN_SMB and READ_EN
    • A full channel registers dump of a retimer channel for when issue is observed.

    Either a USB2ANY or DPS_DONGLE is required to communicate to the DF111 retimer with SigCon Architect GUI.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • Hi Rodrigo,

    Thank you very much for your reply, and I would confirm with our customer.

    Best regards

    kailyn

  • Hello Rodrigo,

    Attached file is the HEX file generated with SigCon Architect GUI. In addition, the customer hasn't bought USB2ANY or DPS_DONGLE, so he has no idea to check the registers when issue is observed.

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/SFI.7z

    2728.schematic.docx

    Best regards

    Kailyn

  • Hi,

    Thank you for providing the customer info. The schematic looks ok. EN_SMB and READ_EN_N appear to be configured correctly for SMBus Master Mode.

    I think the issue might be related to CDR rate configuration. SFI should involve operation at 10.3125Gbps. The customer should update their Hex file to ensure channel registers 0x60 thru 0x64 are configured correctly for 10.3125G rate. Refer to table below.

    Table. Programming Values for Common Data Rates

    VCO Group 0 (GHz)

    VCO Group 1 (GHz)

    Register 0x60

    Register 0x61

    Register 0x62

    Register 0x63

    Register 0x64

    9.8304

    9.8304

    0x26

    0xB1

    0x26

    0xB1

    0xFF

    9.95328

    9.95328

    0xC4

    0xB1

    0xC4

    0xB1

    0xCC

    10.0

    10.3125

    0x00

    0xB2

    0x90

    0xB3

    0xCD

    10.51875

    10.51875

    0x98

    0xB4

    0x98

    0xB4

    0xDD

    10.70957

    11.0957

    0x8C

    0xB5

    0x7A

    0xB7

    0xDE

    Cordially,

    Rodrigo

  • Hello Rodrigo,

    Our customer has changed the Register  0X60~0X64, but it has not resolved the problem and the LOCK is always low. So please help to analyze again.

    Attached is .HEX file. 

    SFI-1123 (1).zip

    Best regards

    Kailyn

  • Hi,

    For the sake of debug, I would recommend to evaluate the following retimer channel register settings while configuring the retimer using SMBus Slave Mode.

    • Try manually forcing CTLE = 0x00 (lowest EQ boost value)

    REG

    Value

    Comment

    0x31

    0x00

    Set Adapt mode 0

    0x2D

    0x88

    Enable EQ override

    0x03

    0x00

    Set EQ = 00

    0x3A

    0x00

    Set EQ = 00

    0x0A

    0x1C

    Puts the CDR into RESET

    0x0A

    0x10

    Releases the CDR from reset

    • Try disabling the Single Bit Transition (SBT) function by setting 0x0C[3]=0
    • Try disabling the PPM check by setting 0x2F[2]=0

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer