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DP83822I: False carrier sense latch in DP83822 when connected to LAN9500

Hao Wang14
Expert 4415 points
Part Number: DP83822I

Hi Team,

DP83822 is transformerless configuration and connected to LAN9500, both of DP83822 and LAN9500 are configured to fixed 100Mbps and auto-crossover.

However, it's found that DP83822 shows to be link up and link down continuously, while LAN9500 is always link up.

When linked up, the 0x01 registers value is 0x4805 which tells that the signal detect is 0 and false carrier sense latch is 1, then it will become to link down. The registers value when the link is up and down is as below:

My questions are:

1. What does the false carrier sense mean here? What are the possible reasons for this fault?

2. The parallel detection fault also happens, what's the possible reason?

3. Is there any recommendation for this kind of continuous link up and down such as register configuration? 

Thanks and Best Regards!

Hao

  • 0
    TI__Expert 5425 points

    Hi Hao,

    Is the link partner (LAN9500) capable of capacitive coupling? If so, can you try the following:

    1. Make sure coupling capacitors are 0.1 uf
    2. Write 0x0024 to register 0x0404

    Let me know this fixed your issue, or if you still have issues.

    Regards,

    Adrian Kam

  • 0 in reply to Adrian Kam
    TI__Expert 4415 points

    Hi Adrian Kam,

    LAN9500 is connected directly with DP83822 with 0.1uF capacitor, and register 0x0404 is set to 0x0024, the issue still exists, 

    When linked up, the 0x0010 registers value is 0x4805 which tells that the signal detect is 0 and false carrier sense latch is 1, then it will become to link down.

    Also, the 0x0012 register is 0xe200.

    Could you please help explain:

    1. What does the false carrier sense mean here? What are the possible reasons for this fault?

    2. The parallel detection fault also happens, what's the possible reason?

    3. What's the reason for register 0x0012 link interrupt? 

    Thanks and Best Regards!

    Hao

  • 0 in reply to Hao Wang14
    TI__Expert 5425 points

    Hi Hao,

    To answer your questions:

    1. The false carrier sense latch bit in register 0x10 is set to 1 whenever a false carrier event has occurred, which essentially means there was a packet error.
    2. Parallel detection is a means for a PHY in auto-negotiation mode to link-up with a link partner that is not setup in auto-negotiation mode. If the parallel detection fault bit is raised, that means there was an error during the process.
    3. The link interrupt in 0x0012 is there to signal a change in link status. The signal could, for example, be used for some logic application on the processor side.

    Can you provide your schematic? This would help us with the debugging process.

    Regards,

    Adrian Kam

  • 0 in reply to Adrian Kam
    TI__Expert 4415 points

    Hi Adrian,

    I will send the schematic through email. Thanks!

    Best Regards!

    Hao

  • 0 in reply to Hao Wang14
    TI__Expert 5425 points

    Hi Hao,

    If you click on my E2E profile, my email should now be displayed. You can send the schematic to that email.

    Regards,

    Adrian Kam