SN65DSI84: display have ghosting and serrated

HI,Could you give us some suggestion? dsi84 cause,or DSI parameter cause? Thank you all

Hi,

Please go through the below FAQs and make sure you're correctly configuring the device:

https://e2e.ti.com/support/interface/f/138/t/918890

https://e2e.ti.com/support/interface/f/138/t/852871 

Regards,

I.K.

Thank you ,the issue have been solved.

yes,I checked details as FAQs,and discussed with someone ,modify 0x1A bit6,eventually solved the issue.But we still have a question.

Our panel is 1920X1080, We test dsi84's input DSI clock is about 200M,and dsi84's output LVDS clock is about 40M,this is only half of pane requirement,the panel can display normally.And it display unstably  sometime when reboot ,display black screen.How should I handle this point?Thank you.

Hi Cheng,

Can you share you display panel datasheet as well as the .dsi file output from the DSI-Tuner (or just post screenshots of the settings you entered into each tab of the tool)?

Regards,

I.K. 

VL-FS-COG-VLSZT024-05 REV(1)_14.6寸.zipYes,panel datasheet please refer to attached file "VL-FS-COG-VLSZT024-05 REV(1)_14.6寸.pdf",but it don't have precise horizon/vertical parameter,I write these parameter as website.The .dsi file refer to attache file "1124.dsi",except {0x1A, 0x43}.We think dsi clock is decided by SOC output, not decided by dsi84,right?Thank you1124.zip

Hi Cheng,

The settings in the .dsi file you provided are not quite correct. Please reference this FAQ again: https://e2e.ti.com/support/interface/f/138/t/918890 for single DSI to dual LVDS, note how the horizontal DSI parameters have to be double that of the horizontal LVDS parameters. For precise horizontal/vertical parameters it would be best to consult with the display panel OEM.

Correct, the DSI CLK is decided by the SOC output, but you still need to put the correct frequency into the DSI-Tuner as there is a register that configures the PLL based on the DSI CLK frequency.

Regards,

I.K.  

yes,you are right.The horizontal DSI parameters have to be double that of the horizontal LVDS parameters,we have modify this, both DSI tuner para and soc output para.

The clock problem have the same result.Could you have some suggestion?Thank you!

Have you checked that the DSI output from your SoC exactly match what you put into the DSI-Tuner (CLK frequency, active pixels, blanking pixels, etc.)? 

You can check #4 on this FAQ as well to verify: https://e2e.ti.com/support/interface/f/138/t/852871 

The line time you measure should match the line time shown in the Outputs tab of the DSI-Tuner. 

Regards,

I.K.