DS90UB941AS-Q1: Two question on SPLIT MODE and PLL reset function

Zhanpeng Li

Part Number: DS90UB941AS-Q1

Hi team,

we have two quesiton on DS90UB941AS-Q1:

1.RST_PLL_FREQ

could you help us understand the Reset mechanism on RST_PLL_FREQ? how much frequency change will triggle PLL be reset? if we set this bit to 0, is there any protential risk on product design?

2. SPLIT MODE Usage:

Customer is working on evluate the SPLIT MODE of DS90UB941. The requirement is to use this serializer to output two wires to DS90UH948 as the deserializer for two identical displays.

Current problem: There is no problem when 941 drives only one screen. When set to split mode, the i2c register of 948 cannot be accessed, but the link status of 948 is normal.

Support need: could you help provide us with the pseudo-code for the demo configuration of split mode; currently this way to drive two exactly the same screen is supported (the screen is developed by a third party, its configuration is exactly the same, and the i2c address is also the same)

Brandon

over 4 years ago

0 Hamzeh Jaradat over 4 years ago

TI__Guru** 107510 points

Hello Zhanpeng,

please check this AppNote and this AppNote where you can find answers to all your questions.

0 Zhanpeng Li over 4 years ago in reply to Hamzeh Jaradat

TI__Intellectual 2140 points

Hi Hamzeh,

For question 1, i did not find the answer i may need, could you help?

Brandon

0 Casey McCrea over 4 years ago in reply to Zhanpeng Li

TI__Guru** 103215 points

Hello Brandon,

The degree of frequency change that will result in a PLL reset is not a tightly controlled parameter and depends on the PLL characteristic across operating frequency. Is there a specific reason why you would like to disable this default setting? Generally we recommend to keep it default for best performance.

Best Regards,

Casey

0 Zhanpeng Li over 4 years ago in reply to Casey McCrea

TI__Intellectual 2140 points

Hi Casey,

i think the reason is related to another question we solved in customer. I attch the link below:

https://e2e.ti.com/support/interface/f/138/t/956229

we solve the question by setting the RST_PLL_FREQ back to default, which do not dectect the frequency. if we set the RST_PLL_FREQ to 1, the problem will happen. customer would like to know if they default the RST_PLL_FREQ, what else may influence the system?

also,could you help us understand the Reset mechanism on RST_PLL_FREQ? if we set this bit to 0, is there any protential risk on product design?

Brandon

0 Casey McCrea over 4 years ago in reply to Zhanpeng Li

TI__Guru** 103215 points

Hello Brandon,

I don't believe this is the correct way to solve the issue and there is something else underlying which needs to be resolved. What clock mode are you using for the 941AS? PCLK from DSI clock or PCLK from external reference clock mode?

Best Regards,

Casey

0 Zhanpeng Li over 4 years ago in reply to Casey McCrea

TI__Intellectual 2140 points

Hi Casey,

the PCLK is from external reference clock mode. and we don't find any interrupt on external clock signal.

i think what customer really need is help analysis the risk on this solution and the Reset mechanism on RST_PLL_FREQ.

By the way, i believe the default on RST_PLL_FREQ is 0. we change to 1, and problem shows. for now, we just change back to 0 and problem solve for now.

Brandon

0 Casey McCrea over 4 years ago in reply to Zhanpeng Li

TI__Guru** 103215 points

Hello Brandon,

We have not validated such a workaround and I suspect that the underlying cause of your issue here could lead to other failures down the road so we do need to investigate why that is happening. Can you please share a schematic for this design for review? You can share via internal email if you would like

Best Regards,

Casey

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DS90UB941AS-Q1: Two question on SPLIT MODE and PLL reset function