DS250DF810: DS250DF810 CAL_CLK_IN application problems

user6304695

Part Number: DS250DF810

Hi：

I have some questions about CAL_CLK_IN@DS250DF810 applications，please help answer

Q1：CAL_CLK_IN input clock Tr/Tf(rise/fall Time) requirements？

Q2：The first retimer CAL_CLK_OUT connect the second retimer CAL_CLK_IN，is there a problem with this application? have you actually tested it？

Q3：retimer 8-Channel connect 2*100g . is there any constraint on Lane remapping？

thanks

CAL_CLK_IN

0 user6304695 over 4 years ago

Hi：

Can you help me reply?

Thank you

0 Rodrigo Natal over 4 years ago in reply to user6304695

Hi, see my inputs below.

Q1：CAL_CLK_IN input clock Tr/Tf(rise/fall Time) requirements？

The only electrical requirements for CAL_CLK_IN are included below. There is no strict rise/fall time requirement

PARAMETER		TEST CONDITIONS	MIN TYP MAX			UNIT
CLKf	Calibration clock frequency			25		MHz
CLKPPM	Calibration clock PPM tolerance		-100		100	PPM
CLKIDC	Recommended/tolerable input duty cycle		40%	50%	60%
CLKODC	Intrinsic calibration clock duty cycle distortion	Intrinsic duty cycle distortion of chip calibration clock output at the CAL_CLK_OUT pin, assuming 50% duty cycle on CAL_CLK_IN pin.	45%		55%
CLKnum	Number of devices which can be cascaded from CAL_CLK_OUT to CAL_CLK_IN	Assumes worst-case 60%/40% input duty cycle on the first device. CAL_CLK_OUT from first devuce connects to CAL_CLK_IN of second device, and so on until the last device.		20		N/A

Q2：The first retimer CAL_CLK_OUT connect the second retimer CAL_CLK_IN，is there a problem with this application? have you actually tested it？

No issue at all. TI has tested this configuration extensively. In addition, multiple customers are using it on system

Q3：retimer 8-Channel connect 2*100g . is there any constraint on Lane remapping？

None.

Cordially,

Rodrigo Natal

HSSC Applications Engineer

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