DP83640: Synchronous clock output

Hi Hariharan,

If I understand correctly, you are trying to perform rate correction, as described by section 3.1 of the linked app-note:

Can you describe your setup in more detail? What was the exact script used to program the PHY?

Thank you,

Nikhil

Thanks for your reply Nikhil, S but its not 3.1,its 3.2 Phase allignment I did everything as in 3.2 ,ie setting those registers and also base registers like BMCR and PAGESEL. But I didn't get the 10Mhz in output clk. I did verilog code for MDC,MDIO serial management for register configuration.

I just had clarification in for Synchronous clock output whether those registers is sufficient or I need to assign some more registers

Hi Hariharan,

You may refer to the linked thread for additional information and a more detailed procedure: 

Please let me know if you have any further questions.

Thank you,

Nikhil

Thanks for your reply ,will see through it.

Just one more doubt if I want to synchronize two boards,

two board will have its own fpga clock, an oscillator for ref clock, a transmit clock from phy and receive clk.

For MII mode we use only three clock a reference clk, a transmit clk, a receive clk.

If I transfer packet timestamp to slave ,what is my master clock, how the slave clock know this is master clock.If I use 100Mbps Tx clk is 25Mhz,MDC clk is 25Mhz then where I am saying my master clock.

If I want to use a board as master and slave, is that I can use only RMII. Because in MII there is no master and slave mode.

Hi Hariharan,

You are correct, if you wish to use a master/slave configuration, RMII interface must be used. I'm not clear on your other question. What is your hardware setup and what MAC interface are you using?

Thank you,

Nikhil

THanks for ur reply nikhil,

I want to synchronize three fpga boards one as master and other two as slave, so you are saying that, to use this I should configure all three boards in RMII interface not in MII.

MY previous question is that according to the master clock, the slave clock will adjust right. what is that master clock, exactly where I am giving that clock.

(you can say it will adjust according to timestamp, S it will .But my question is the clock with which the time stamp is send, is it the master clock.)

In MII we use only three clk REFCLK,TX_CLK,RX_CLK.I am not giving the master clock here then how the slave adjust its clock.

My hardware setup is ZYNQ board and it has DP83640.I thought that I can use MII mode but there is no master or slave configuration.

Hi Hariharan,

We are looking into your questions and will provide feedback by Monday next week.

Thank you,

Nikhil

As I said in the pervious question to configure the clock out  pin through (250MHz divide by an integer N value)by changing the values in PTP_COC register. There is no change in clock out pin, I got continuously 25MHz frequency only. so I tried to check the register value by read  operation. But it gives 16 bit's of 0's. what could be the problem. Either I have to reduce the MDC clock frequency or it doesn't take the value what I give

our motive to syn more than two  FPGA boards for that first we try to configure the clock out pin. To configure and check the above operation(config clock out pin) I used data and clock pin's in DP83640.

1.MDC pin

2.MDIO pin

3.RESET pin

4.CLOCK_OUT pin

5.TX_CLK pin

Thanks for your reply Nikhil, Thanks a lot. Will try it.

No problem! I hope this helped. If you have any further questions you may open a new thread.

Thank you,

Nikhil