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DS90UH941AS-Q1: splitting mode---establish FPD-LINK connection for port1

semiyd
Expert 1600 points
Part Number: DS90UH941AS-Q1

Hi team,

We have a simple application scenario. The image of 3840 * 1080 * 50FPS is input from dsi0 and divided into two symmetrical images, which are output from FPD-LINK port 0 and port 1 respectively. Port 0 / 1 is in single lane mode, and both are attached to 948 deserializer. The I2C address of both deserializer are 0x2c. The I2C of port 0 can be accessed and the split graph can be displayed normally, but the I2C of port 1 is not working. Here is my original idea:

I switch the I2C access port through the 0x1E register, set 0x05 to access port0's I2C, and set 0x06 to access I2C of port1. And I enabled the I2C_PASSTHROUGH of both port0 and port1. Is this right?

If not, how do you need to configure to enable port 1? Port 0 and port 1 have exactly the same I2C address, Is this a problem? 

  • 0
    TI__Guru** 108360 points

    Hello Semiyd,

    please check this AppNote and this AppNote where you can find answers to all your questions.

  • 0 in reply to Hamzeh Jaradat
    Expert 1600 points

    Hi Hamzeh，

    Can you answer the questions directly?  I have already read the AppNote, but it did not resovle my problem..That's why I am here..

  • 0 in reply to semiyd
    TI__Guru** 108360 points

    Hello Semiyd,

    Then allow me few days untill I come back to you.

  • 0 in reply to Hamzeh Jaradat
    TI__Guru** 108360 points

    Hello Semiyd,

    Your thinking is correct.The 941AS reg 0x1E (TX_PORT_SEL) controls access to the two sets of specific registers, i.e. Port0 registers and Port1 registers.

    Setting bit0 (TX_PORT0_SEL) or bit1 (TX_PORT1_SEL) in this register will allow a read of the register for the selected port. If both bits are set, port1 registers will be returned. Writes to ports will occur on a port where the select bit is set, allowing simultaneous writes to both ports if both select bits are set.


    Setting reg 0x1E[2] (PORT1_I2C_EN) will enable a second I2C slave address, allowing access to the second port registers through the second I2C address. If this bit is set, the TX_PORT0_SEL and TX_PORT1_SEL bits will be ignored.

    Note: Port1 registers are only available in Independent 2:2 and/or Splitter modes. If these modes are not enabled, all accesses to these registers will be to port 0  registers.

    The sequence for doing this can look like following example:

    Write reg0x1E = 0x01 //Select FPD-Link III Port 0
    Write reg0x1E = 0x04 //To use I2D ID+1 for FPD-Link III Port 1 register access
    Write reg0x1E = 0x01 //Select FPD-Link III Port 0
    Write reg0x03 = 0x9A //Enable I2C_PASSTHROUGH, FPD-Link III Port 0
    Write reg0x1E = 0x02 //Select FPD-Link III Port 1
    Write reg0x03 = 0x9A //Enable I2C_PASSTHROUGH, FPD-Link III Port 1