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SN65LVDS31: Open Input

Part Number: SN65LVDS31
Other Parts Discussed in Thread: SN65LVDS33

I am using SN65LVDS31 as a line driver and sn65lvds33 as a receiver. Both components are in the same module but on different Boards. There are 4 PCBAs in the module and driver is on 1st and Receiver is on the 4th PCBA. Total length of the Traces will be around 80 cm. 

Both chips are supplied by same 3V3-DC-DC supply. I hope this is already a meant application for these two components.

For driver component, I add a pull down 4k7 resistor for open inputs and for related output I directly terminate it with 100 ohm at the output of the gate driver. Do you think is this the right approach? 

Thank you for your help

Best Regards

  • Hi Onur,

    Unused inputs to the SN65LVDS31 should be left open circuited. All inputs are internally pulled down to ground with approximately a 300-kΩ resistance. You can leave the outputs open too.

    Regards,

    I.K. 

  • Good morning,

    thank you for the answer,

    I am using SN65LVDS33 as a receiver. For unused LVDS inputs and single ended outputs of SN65LVDS33, should I leave them as open?

    Also in the datasheet, I see the TTLs are 5V compatible but max recommended value is 5V and absolute max is 6V. 

    Is 5V in the datasheet has no range? My enable signal may come in between 5V to 5.2V.  

    Best Regards

    Onur

  • Hi Onur,

    SN65LVDS33 also has fail-safe, so you can leave unused LVDS inputs and single-ended outputs open.

    For the TTL signals, the recommended operating conditions for Vih is 2 to 5 V. The absolute max rating is 6 V, which just means the device will not be damaged for voltages up to 6 V. However, it is recommended to keep ranges within the recommended operating conditions specified in the datasheet.

    Regards,

    I.K. 

  • Good morning,

    We are using this SN65LVDS31 and SN65LVDS33, I couldn't find an info how strict I should match this P-N(in pair) if we would like to use these components with full bandwidth. (around 400Mbps)

    Do you have an application note or suggestion for this?

    Best Regards

    Onur

  • Hi I.K.

    Thanks for the update,

    I am aware of what absolute max means, so basically what you suggest me is not connect to TTL signals anything above 5V.

    Even though I set my supply output to 5V, there is always some tolerances from ICs and feedback resistors and it can always be a bit more than 5V un less I set the supply output intentionally below 5V and cover the tolerances. 

    I know it is stated as 5V max in datasheet but do you think you could double check it if the recomended max for these TTL signals are really 5V max and there is no margin?

    Thank you very much in advance for your help.

    Best Regards

    Onur

  • Hi Onur,

    You can reference this application note for guidelines on PCB and P-N matching: https://www.ti.com/lit/an/snla302/snla302.pdf. It was written for SerDes but is applicable to all LVDS.

    In regards to the 5V max in the datasheet, we cannot recommend anything outside of the recommended specifications as these were the conditions the device was characterized in. There may be some margin but we cannot guarantee correct operation across process and temperature.

    Regards,

    I.K. 

  • Good thanks,

    I used this 30ps skew rule.

    Is there any application note how to place the 100 ohm termination resistors to the PCB.

    On PCB, LVDS signals which are routed to sn65lvds33 needs to go to IC pins first and then terminated with 100 ohm or first to 100 ohm resistors and then to IC?

  • Hi Onur,

    The termination resistor should match the characteristic impedance of the transmission line, and should be placed as close to the receiver input pins as possible. The LVDS signals will go to the termination resistor first and then to the IC.

    Regards,

    I.K.