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XIO2001: XIO2001 REFCLK, PCLK, Perest

Frank Xiao
Genius 12055 points
Part Number: XIO2001

Hi team,

My customer is using the XIO2001 now. We want to check whether the PCLK will be ok after the PEREST ok. Do we have some methods to make the pcie pclk ok when PCI-E refclk is ok(no matter the Perest)? Thanks.

  • 0
    TI__Guru* 93670 points

    Hi Frank,

    Please note power up and power down sequencing noted in the data sheet(section 6.12). We need to make sure we meet these requirements.

    After PERSTbar, reg 0xD8 - output clock control - gets reseted. The default value or after PERSTbar this register is at 0x00. This setting enables the PCLK outputs. In summary as long we do the power sequencing as noted in the data sheet, PCLK outputs would be valid on rising edge of the PERSTbar.

    Regards,, Nasser