DP83869HM: DP83869HMRGZT No Ping and No Data Communication But PHY is able to auto Negotiate

Dear ALL,

Am Balakrishna J,

In my custom Zynq Ultra Scale MPSOC Board board I Have Connected 2 Ethernets on PS Side and 1 Ethernet in PL side 

PL Side Ethernet is Working Fine...…..

2 Ethernets on PS Side are Working in Peta linux  

(Configuration is RGMII to Copper )

But these Ethernets are not working in Xilinx Vitis Baremetal (Lwip) Both has separate MDIO and MDC Lines 

when I Debug 

the Following is the all Registers data  

-----lwIP TCP echo server ------
TCP packets sent to port 6001 will be echoed back
Start PHY autonegotiation
Waiting for PHY to complete autonegotiation.
autonegotiation complete
link speed for phy address 13: 1000
============================= XEmacPs_PHYSetup Start =============================
In XEmacPs_DetectPHY: Detected PHY address is 13
Phy Addr:13 Reg Addr :0x0 Reg Data 0x1140
Phy Addr:13 Reg Addr :0x1 Reg Data 0x796D
Phy Addr:13 Reg Addr :0x11 Reg Data 0xAC02
Phy Addr:13 Reg Addr :0x1F Reg Data 0x0
Phy Addr:13 Reg Addr :0x1 Reg Data 0x796D
Phy Addr:13 Reg Addr :0x1F Reg Data 0x0
Phy Addr:13 Reg Addr :0x09 Reg Data 0xB00
Phy Addr:13 Reg Addr :0x0A Reg Data 0x7800
Phy Addr:13 Reg Addr :0x11 Reg Data 0xAC02
Phy Addr:13 Reg Addr :0x6E Reg Data 0xFFFF
TP Phy Addr:13 Reg Addr :0xE Reg Data 0xC0F

(Value of Reg Address  : Reg Data)

Value of 0x25 : 0x480
Value of 0x2C : 0x141F
Value of 0x2D : 0x0
Value of 0x2E : 0x221
Value of 0x31 : 0x0
Value of 0x32 : 0xD3
Value of 0x33 : 0x0
Value of 0x37 : 0x0
Value of 0x39 : 0x0
Value of 0x3A : 0x0
Value of 0x4F : 0x200
Value of 0x6E : 0x20D0
Value of 0x6E : 0x20D0
Value of 0x86 : 0xA8
Value of 0x134 : 0x1000
Value of 0x135 : 0x0
Value of 0x86 : 0xA8
Value of 0x170 : 0xC0F
Value of 0x180 : 0x752
Value of 0x181 : 0xC850
Value of 0x182 : 0x5326
Value of 0x183 : 0xA01E
Value of 0x184 : 0xE976
Value of 0x185 : 0x19CF
Value of 0x190 : 0x0
Value of 0x191 : 0x0
Value of 0x192 : 0x0
Value of 0x193 : 0x0
Value of 0x194 : 0x0
Value of 0x195 : 0x0
Value of 0x196 : 0x0
Value of 0x197 : 0x0
Value of 0x198 : 0x0
Value of 0x199 : 0x0
Value of 0x1A4 : 0x0
Value of 0x1A5 : 0x0
Value of 0x1A6 : 0x0
Value of 0x1DF : 0x40
Value of 0x1E0 : 0x417A
Value of 0xC00 : 0x140
Value of 0xC01 : 0x6149
Value of 0xC02 : 0x2000
Value of 0xC03 : 0xA0F1
Value of 0xC04 : 0x20
Value of 0xC05 : 0x0
Value of 0xC06 : 0x0
Value of 0xC07 : 0x2001
Value of 0xC08 : 0x0
Value of 0xC18 : 0x1FF
Value of 0xC19 : 0x10
Value of 0x32 : 0xD3
============================= XEmacPs_PHYSetup Done =============================
Board IP: 192.168.1.10
Netmask : 255.255.255.0
Gateway : 192.168.1.1
TCP echo server started @ port 7

Application is running Fine But NO Ping and No Data Sharing is happening 

any suggestion by looking at above register read data for establishing  successful communication is very much help full for me 

extended Reg address reading Procuder is followed as per data sheet 

cust_reg_add =0x25;
XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddress, 0x0D, 0x001F);//
XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddress, 0x0E, cust_reg_add);//
XEmacPs_PhyWrite(EmacPsInstancePtr, PhyAddress, 0x0D, 0x401F);//

XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddress, 0x0E, &cust_reg_data);//extended address
xil_printf("Value of 0x%x : 0x%x\r\n",cust_reg_add,cust_reg_data);

like wise all register am reading and Read data attached above 

thank you 

Regards 

Balakrishna J 

Hi Balakrishna,

We are looking into this issue and will provide feedback by Tuesday next week.

Thank you,

Nikhil

Hi Balakrishna,

I noticed that in the initial register read section I see the following line "Phy Addr:13 Reg Addr :0x6E Reg Data 0xFFFF" and later on I see "Value of 0x6E : 0x20D0." Are you reading two different values for register 0x6E when reading at different times? 

Can you confirm the following settings are desired?

• Auto-negotiation enabled, all speeds
• Full/Half Duplex
• RGMII to Copper
• Disable Link Loss pass through

Can you also provide a schematic?

Thank you,

Nikhil

Dear Sir,

Thank you for Response,

Please Do not Consider This Print Statement ====> Phy Addr:13 Reg Addr :0x6E Reg Data 0xFFFF"  am Wrongly reading here ,, Forgot to remove these line in the post

This is the Valid read Value "Value of 0x6E : 0x20D0."

Can you confirm the following settings are desired? Yes Sir These the Settings Required For and accordingly Pull up/down Resister are connected.

• Auto-negotiation enabled, all speeds
• Full/Half Duplex
• RGMII to Copper
• Disable Link Loss pass through

any connection need to be altered for establishing for  successful communication Please Suggest sir we will Update accordingly. But same Configuration is Tested under Peta Linux Environment  (OS) Which is working Fine

IF I connect Ethernet Through a unmanage Switch (Basically a 8 port router ):  bare metal code error comes as  Auto negotiate Error and it gives Phy set up Failure

IF I connect Ethernet Cable to MY PC directly ::  PHY  will Auto negotiate But there will not be  PING and Data Sharing am running simple Lwip Echo server example from Xilinx Vitis SDK

-----lwIP TCP echo server ------
TCP packets sent to port 6001 will be echoed back
Start PHY autonegotiation
Waiting for PHY to complete autonegotiation.
autonegotiation complete
link speed for phy address 13: 1000

Board IP: 192.168.1.10
Netmask : 255.255.255.0
Gateway : 192.168.1.1
TCP echo server started @ port 7

============================= XEmacPs_PHYSetup Start =============================
In XEmacPs_DetectPHY: Detected PHY address is 13
Phy Addr:13 Reg Addr :0x0 Reg Data 0x1140
Phy Addr:13 Reg Addr :0x1 Reg Data 0x796D
Phy Addr:13 Reg Addr :0x11 Reg Data 0xAC02
Phy Addr:13 Reg Addr :0x1F Reg Data 0x0
Phy Addr:13 Reg Addr :0x1 Reg Data 0x796D
Phy Addr:13 Reg Addr :0x1F Reg Data 0x0
Phy Addr:13 Reg Addr :0x09 Reg Data 0xB00
Phy Addr:13 Reg Addr :0x0A Reg Data 0x7800
Phy Addr:13 Reg Addr :0x11 Reg Data 0xAC02
TP Phy Addr:13 Reg Addr :0xE Reg Data 0xC0F

Value of 0x25 : 0x480
Value of 0x2C : 0x141F
Value of 0x2D : 0x0
Value of 0x2E : 0x221
Value of 0x31 : 0x0
Value of 0x32 : 0xD3
Value of 0x33 : 0x0
Value of 0x37 : 0x0
Value of 0x39 : 0x0
Value of 0x3A : 0x0
Value of 0x4F : 0x200
Value of 0x6E : 0x20D0
Value of 0x6E : 0x20D0
Value of 0x86 : 0xA8
Value of 0x134 : 0x1000
Value of 0x135 : 0x0
Value of 0x86 : 0xA8
Value of 0x170 : 0xC0F
Value of 0x180 : 0x752
Value of 0x181 : 0xC850
Value of 0x182 : 0x5326
Value of 0x183 : 0xA01E
Value of 0x184 : 0xE976
Value of 0x185 : 0x19CF
Value of 0x190 : 0x0
Value of 0x191 : 0x0
Value of 0x192 : 0x0
Value of 0x193 : 0x0
Value of 0x194 : 0x0
Value of 0x195 : 0x0
Value of 0x196 : 0x0
Value of 0x197 : 0x0
Value of 0x198 : 0x0
Value of 0x199 : 0x0
Value of 0x1A4 : 0x0
Value of 0x1A5 : 0x0
Value of 0x1A6 : 0x0
Value of 0x1DF : 0x40
Value of 0x1E0 : 0x417A
Value of 0xC00 : 0x140
Value of 0xC01 : 0x6149
Value of 0xC02 : 0x2000
Value of 0xC03 : 0xA0F1
Value of 0xC04 : 0x20
Value of 0xC05 : 0x0
Value of 0xC06 : 0x0
Value of 0xC07 : 0x2001
Value of 0xC08 : 0x0
Value of 0xC18 : 0x1FF
Value of 0xC19 : 0x10
Value of 0x32 : 0xD3

here is the schematic sir for your reference

Hoping for Best and Quick Reply sir

Thank you

regards

Balakrishna J

Hi Balakrishna,

Please see my feedback below:

• Remove pull-ups on center-taps of transformers. Refer to Figure 111 in datasheet for schematic diagram.
• JTAG_TDO should be left floating for RGMII to Copper mode. If strap resistors are placed, it may be strapping device to different Op Mode.
• Clock: refer to Figure 110 in datasheet for correct clock implementation. May need loading capacitors. Confirm clock source is compatible. 

Please let me know if these changes improve device performance.

Thank you,

Nikhil