Hi Support team,
We have Virtex 7 FPGA interfaced with DP83867 PHY in one of our design.
PHY reset pin is externally pull up with 2.2K VDDIO supply. We want to know the internal power on reset time duration of PHY.
And PHY power on sequence is as below.
VDD1P0 = 1v
VDDIO = 1.8v
VDDA2P5 =2.5v
Please let us know the power on reset time duration and required power sequencing for the DP83867 PHY
Thanks & regards,
Divya