TLK2711EVM-CVAL: How to meet TLK jitter requirement?

Hi,

   We are doing the interoperability test between TLK2711 and Microchip RTG4 FPGA devices. Here we aim to send the PRBS-7 pattern at data rate of 2.5 Gbps from TLK2711 TX to RTG4 RX and through far end loopback send it back to TLK2711 Rx. But PRBS_PASS signal is never high (always toggling). We also tried simplex tests (no loopback) as follows:

1. Transmitted PRBS-7 pattern from TLK2711 Tx to RTG4 Rx successfully. CDR of RTG4 SERDES is locked with cumulative errors count zero.
2. Transmitted PRBS-7 pattern from RTG4 Tx to TLK2711 Rx unsuccessfully. PRBS_PASS signal always toggling.

We also noticed that TLK2711 data sheet says that TXCLK jitter peak to peak is 40 ps but we are not able to meet that requirement. We are giving 125 Mhz clock from SI5338 clock generator board and when we tried to measure the jitter of this clock its PJrms value is 19.8 ps which if we multiply to Crest factor of 14 (as applicable for the bit rate of 1e-12 for clock signals) gives us peak to peak value of 278 ps (way higher than the data sheet specification of 40 ps). Please let us know how to meet TLK jitter requirement?

Also VICM (common mode voltage) of both TLK2711 and RTG4 devices are different. VICM for TLK2711 Rx, Tx is 1250 mV typical where as for RTG4 Tx and RTG4 Rx it is 20mV and 150 mV typical respectively.

What could be the possible causes of this behavior of not able to see PRBS_PASS signal status as high at the TLK2711 side? Please note that we tried tlk2711 internal loopback and it is consistently high.

Thanks

Deepak