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DS90UB935-Q1: Question about ALARM_CSI_EN(0x1C)

Yuta Kurimoto
Genius 11365 points

Part Number: DS90UB935-Q1
Other Parts Discussed in Thread: DS90UB954-Q1, , DS90UB953-Q1

Hello Team,

I got question from customer about the ALARM_CSI_EN(0x1C). This register can enable each alarm.

Q. If the CSI-2 No Frame Valid Alarm(Bit5) was enabled and the alarm was triggered, which register indicate the exist of the Alarm?

Q. If the DPHY_SYNC_ERR Alarm(Bit4) was enabled and the alarm was triggered, which register indicate the exist of the Alarm?(I believe 0x5E bit 7,6,3,2 register?)

Q. If the DPHY_CTRL_ERR Alarm(Bit3) was enabled and the alarm was triggered, which register indicate the exist of the Alarm?(I believe 0x5E bit 5,1 register?)

Q. If the CSI_ECC2 ERR Alarm(Bit2) was enabled and the alarm was triggered, which register indicate the exist of the Alarm?(I believe 0x5D bit 1 register?)

Q. If the CSI-2 Checksum Error Alarm(Bit1) was enabled and the alarm was triggered, which register indicate the exist of the Alarm?(I believe 0x5D bit 2 register?)

Q. If the CSI-2 Length Error Alarm(Bit0) was enabled and the alarm was triggered, which register indicate the exist of the Alarm?(I believe 0x5D bit 3 register?)

Thanks,

Yuta Kurimoto

  • 0
    TI__Expert 5480 points

    Hi Yuta, 

    The alarm will be flagged on the DES. For example, if you pair with the DS90UB954-Q1, registers 0x51-0x54 indicate the alarm status.

    7.4.12 Sensor Status When paired with the DS90UB935-Q1 or DS90UB953-Q1 serializer, the DS90UB954-Q1 is capable of receiving diagnostic indicators from the serializer. The sensor alarm and status diagnostic information are reported in the SENSOR_STS_X registers (0x51 to 0x54 in Table 92). The interrupt capability from detected status changes in sensor are described in Interrupts on Change in Sensor Status. Sensor Status This interrupt condition will be cleared by reading the CAM_INT_RISE_STS and CAM_INT_FALL_STS registers.

    Thanks,
    Sally