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DS90UB947-Q1: 947/948 display flicker

Betty Guo
Expert 7300 points
Part Number: DS90UB947-Q1
Other Parts Discussed in Thread: ALP

Hi team,

customer use 947/948, find some boards have flicker issues in PP stage.

below is test reslut:

1. when flicker, the lock is high

2. use 947 pattern mode:

a. 947 internal clock and internal video timing, display is ok.

b. use SOC external clock, 947 internal video timing, display is ok.

c. use SOC extranl clock and external video timing, display flicker.

3. customer use APL margin analysis, attached file margin_20201209; also attched 947 configur code, file name isp_fpglink.c

4. base on pattern mode test reslut, this issue maybe is SOC video data. but customer don't have any idea how to check it. could you give some suggestions.

also attached issue video, file name is 947 splash. thanks.

7220.947 splash.zip

闪屏_margin_20201209.rar

2630.isp_fpdlink.c
Fullscreen
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#include <common.h>
#define UBOOT_TCON
#include "drivers/tcon/hal_SPHE8388_tcon.h"
#undef UBOOT_TCON
#include "drivers/gpio/sp_gpio.h"
#define DEBUG_ON_OFF
#if defined(DEBUG_ON_OFF)
#define ds90ub947_dbg(fmt, arg...) \
printf(fmt, ##arg)
#else
#define ds90ub947_dbg(...)
#endif
typedef unsigned char u8;
static u8 s3_panel = 1;
#define I2C_START_STOP_DELAY_TIME 20
#define I2C_DATA_DELAY_TIME 20
#define I2C_ACK_DELAY_TIME 100
static void delay_i2c(int cnt)
{
udelay(cnt);
}
static void msleep(int ms)
{
delay_i2c(ms * 1000);
}
#define ADDR_DS90UB947 (0x0C << 1) /*7 bit i2c addr*/
#define ADDR_DS90UB947_2 ((0x0C + 1) << 1) /*7 bit i2c addr*/
#define ADDR_DS90UB948 (0x2C << 1) /*7 bit i2c addr*/
#define ADDR_LP8860 (0x2D << 1) /*7 bit i2c addr*/
#define ADDR_TP 0x24 /*7 bit i2c addr*/
#define DS90UB947_I2C_DEVICE_ID_REG 0x00
#define DS90UB947_I2C_DEVICE_ID 0x18
#define DS90UB948_I2C_DEVICE_ID_REG 0x00
#define DS90UB948_I2C_DEVICE_ID 0x58
#define SCL_PIN 22
#define SDA_PIN 23
#define I2C_SCL_OUT() GPIO_E_SET(SCL_PIN, eHW_GPIO_OUT)
#define I2C_SDA_OUT() GPIO_E_SET(SDA_PIN, eHW_GPIO_OUT)
#define I2C_SDA_IN() GPIO_E_SET(SDA_PIN, eHW_GPIO_IN)
#define I2C_SCL_IN() GPIO_E_SET(SCL_PIN, eHW_GPIO_IN)
#if 0
#define I2C_SCL_H() I2C_SCL_OUT();GPIO_O_SET(SCL_PIN, 1)
#define I2C_SDA_H() I2C_SDA_OUT();GPIO_O_SET(SDA_PIN, 1)
#else
#define I2C_SCL_H() I2C_SCL_IN();{ \
int i; \
for (i = 0; i < 2000; i ++) { \
if (I2C_SCL_GET()){ \
delay_i2c(1); \
if (I2C_SCL_GET()) { \
break; \
} \
}\
} \
}
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0
    TI__Guru** 101590 points

    Hello Betty,

    I have seen similar problem discription before. This is something related to the timing of the incoming signal from the SoC.

    Please have them measure the jitter and the skew on all data lanes with reference to the clock lane.

    I will send you the instrunctions per email.

  • 0 in reply to Hamzeh Jaradat
    TI__Expert 7300 points

    Thanks Hamzeh, I will let customer to measure this.

    one little problem is that, customer test condition maybe is difference with you. for example scope and bandwidth.

  • 0 in reply to Hamzeh Jaradat
    TI__Expert 7300 points

    Hi Hamzeh,

    customer don't have suit scope to measure video data. 

    I want to confirm with you that this issue may relate to the timing of data signal, not relate to 947/948, right?

    customer need to improve the SOC output signal instead of 947/948 setting? any other possible causes? thanks

  • 0 in reply to Hamzeh Jaradat
    TI__Expert 7300 points

    Hi Hamzeh,

    customer have use ALP tools analysis the signal, below is reslut. based on this reslut, do you have comments how to debug next? thanks.

  • 0 in reply to Betty Guo
    TI__Guru** 101590 points

    Hello Betty,

    you are right. This issue is on the timing of  the incoming data signal, not related to 947/948.

    Questions:

    How long is the used cable?

    What is the PCLK?

    The MAP Tool results does not look correct. You can't get complete green window.

  • 0 in reply to Hamzeh Jaradat
    TI__Expert 7300 points

    Hi Hamzeh,

    for video timing, can you give a more specfic parameter about input signal that can match 947? for exampel clock, data jitter or something?

    customer don't have scope to meaure input signals. do you have another methods ?

    I will let customer replay your questions. thanks

  • 0 in reply to Hamzeh Jaradat
    Prodigy 20 points

    Hi Hamzeh,

    Please check below information:

    How long is the used cable?---100 cm

    What is the PCLK?--41Mhz

  • 0 in reply to Hamzeh Jaradat
    Prodigy 20 points

    Hi Hamzeh,

    Please check below:

    How long is the used cable? 

    -> 100cm.

    What is the PCLK?

    --> 41.56Mhz.

     

  • 0 in reply to hongen liu1
    TI__Guru** 101590 points

    Hello Betty,

    Unfortunately, there is no other method to measure this than the High Speed scoope.

    They need to measure the jitter and skew of the input signal. specially D2 because it contains the timing parameters, such as HSync, VSync and DE.