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DS90UB935-Q1: Question about CSI_ERR_DLANE01 (Address 0x5E)

Yuta Kurimoto
Genius 10630 points
Part Number: DS90UB935-Q1

Hello Team,

I have question about the 0x5E bit2(SOT_SYNC_ERROR_0) and bit6(SOT_SYNC_ERROR_1),

I think these registers are flagged when there are uncorrectable Multi-bit error. If this error is occurred, How to deal with it in system level?

And can you let me know how to clear these register? 

Thanks,

Yuta Kurimoto

  • 0
    TI__Expert 5480 points

    Hi Kurimoto-san, 

    SOT Sync Errors are errors with the start of transmission. In the MIPI standard, the D-PHY TX sends a sync sequence as part of the HS start of transmission sequence. You may want to verify the signal integrity from your D-PHY CSI TX to the 935 and also verify your TX is not having issues. The D-PHY standard sync sequence is " ‘00011101’ beginning on a rising Clock edge". You can probe the signal and make sure that the TX is outputting this sequence. 

    If you read 0x5D, does it clear? 


    Thanks

    SAlly 

  • 0 in reply to Sally Cheung95
    TI__Genius 10630 points

    Hello Sally, 

    Thanks for your answer.

    By the way, Which bit should they read in the 0x5D register for clearing the SOT sync error?

    Regards,

    Yuta Kurimoto

  • 0 in reply to Yuta Kurimoto
    TI__Mastermind 37070 points

    Hi Kurimoto-san,

    Your understanding is correct. When you read the register 0x5D error status, did SOT sync error goes way? Please check this, and let us know.

    Aaron