DP83822H: RX Clock output behavior before and after reset - RGMII

Hi Dan,

I am not aware of a 1.25MHz clock on the line so this is an interesting case. Are there any connections on the RX_CLK line that could be causing the disturbance? Does the 25MHz oscillator meet the spec we recommend in our datasheet?

Thanks,

Cecilia

Cecilia Hi , 

thanks for you reply - 

the oscillator meets the spec - 

might we mistakenly entered one of the reserved modes of configuration during the power on - will that explain such clock ?   

a follow up Q - will entering a reserved mode of MAX interface during configuration for a short period (few tens/hundred mS) be destructive to the IC ? 

might it shorten the device expected Life span  ? 

Hi Dan

That could be a possibility. Can you please share the boostraps on your schematic so we can confirm if it is in some test mode?

Also per your second question can you please explain what you mean by max interface?

Thanks,

Cecilia

Cecilia Hi  , 

the bootstraps are as follow (all res are 1%) :

Rx_d3 - open

Rx_d2 - open

Rx_d1 - 2.49K Pull Down

Rx_d0 - 2.49K Pull up

Rx_dv - open

Rx_er - 6.19K PU and 1.96K PD 

Rx_CRS - 13K PU and 1.96K PD

Phy_led_0 - open.

VDDIO = 1.8V

this configuration pins are also connected to the PS portion of a XILINX ZYNQ device - and the error state is while the ZYNQ I/Os are not defined (e.g configuration not done).

regarding my second question - sorry  -had a typo  - I meant a reserved MAC interface configuration ( Tables:11 - 14 in the datasheet )

Cecilia Hi  , 

another follow up question - 

will the phy sample the configuration (bootstrap) pins during powerup - regardless the state of the reset input ? 

E.g - upon rising edge of Vdd will it set a configuration mode/state - even if the reset is held LOW  (device at reset) ?   

thanks.

Dan 

Hi Dan

You can refer to our datasheet to when the PHY samples the latch values of the strap. Table 1 Pin States also shows you what you'd expect the state of the pins to be during reset or active modes

Cecilia

Cecilia Hi , 

the datasheet states "The values of these pins are sampled at power up or hardware reset, through either the RESET pin or bit[15] in the PHY Reset Control Register (PHYRCR, address 0x001F)."

i am still not sure - during the stage of power up - when the reset is held low ( as in the picture below ) will the pins be sampled ? 

Hi Dan,

Pins will be sampled following the latch-in timing diagram, so not when reset is first low. 

Cecilia hi , 

thank you for the clarification, it is much appreciated  .

can we please revisit and address the issue of reserved mode of MAC interface during configuration - what will be the affect/impact on device (short term \ long term?)