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DS90UB954-Q1: TX port Line Count&Line Length

user6259789
Prodigy 230 points
Part Number: DS90UB954-Q1
Other Parts Discussed in Thread: DS90UB933-Q1

Hi Team，

Now we used DS90UB954 coupled with DS90UB933-Q1. In RX port we read register LINE_COUNT_HI (Address 0x73) and LINE_COUNT_LO (Address 0x74) have a fixed number of rows, and LINE_LEN_1 (Address 0x75)&LINE_LEN_0 (Address 0x76) also fixed. But  the next level chip RAA278842 decodes the MIPI signal with an ECC and CRC check error and a hint that H-total is not fixed. So can we fix the number of rows and columns in the output of 954, or is there some error in the middle that leads to a check error(CRC&ECC).

Best regards,

Alec Li

  • 0
    TI__Mastermind 30515 points

    alec,

    can you check more:

    1 how about the reg. 0x4c (dependent on which port is used here), 0x4d / 0x4e?

    2. if the 954 mipi output can be aligned with the following chip in your system?

    regards,

    Steven

  • 0 in reply to Steven(Shenzhen) Shi
    Prodigy 230 points

    Hi Steven，

    Thanks for your reply.

    1. Reg. 0x4c = 0x01, reg. 0x4d we read 0x13 first and then change to 0xb0 and then stabilize at 0x03, reg. 0x4e read 0x45 first and then stabilize at 0x04.

    2.What‘s the MIPI aligned? Now our Layout routing is equal length processing.

    Best regards,

    Alec Li

  • 0 in reply to user6259789
    TI__Mastermind 30515 points

    alec

    1. if camera is linked to port0, and the reg. 0x4d/4e doesn't indicate any error bit, it means our fpd-link channel is robust.

    2. the issue could be from the alignment between 954 output and its following sink. you need make them align such as lane number, lane rate, csi2 clock mode setting etc (contiuous or non-conditous?)

    3. also, you need check if the CSI2 layout has issue or not, such as if it has noise or crosstalk, impedance control...

    regards,

    Steven