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DP83867E: pin#44 INT/PWDN(IO/PU) description

Hironori Yoshimura
Intellectual 1850 points
Part Number: DP83867E

According to another e2e thread, this pin has 9KOhm internal pull up Register to PU.
When my customer use /INT mode, Customer mention /INT is default is high eventhough no-pullup-registance.
When customer implemented external 4.7Kohm, INT signal could not go to enough low level around 1.8 - 1.3V range.
Datasheet recommended 2.2Ko, So I already recommended 2.2Ko pull up instead of 4.7Ko.
Orinigally I understand following.  But please correct right behavior ?
/INT : Output : OD
/PWD: Input: internal 9Kohm pull up.

  • 0
    TI__Genius 16030 points

    Hello Yoshimura-san,

    Yes INT is OD, but I will check if there is an internal resistor pull up enabled during INT functionality also. 

    Also when you say INT pin did not go low enough, was PHY driving the INT pin low that time or was it driven low by some other IC connected to INT bus? 

    --

    Regards,

    Vikram