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DP83822I: Configuring RMII master mode

Kazuki Itoh
Genius 11320 points

Part Number: DP83822I

Hello team,

When sending the data, the DP83822I output data garbled. Receiving is working correctly.

I guess this is due to the something is wrong with PHY configuration for RMII master mode.

Could you please help me to address this issue?

Could you please share us the app note or collaterals to configure DP83822I in RMII master mode (e.g. initial state or register setting)?

In my use case, it is used in RMII master mode and 100BASE.

RMII ref clock (50MHz) is output from RX_D3/GPIO and goes to MCU.

I checked TX_EN was output when sending the data.

Please find the internal link here for the register values right after the PHY configuration and link-up.

Regards,

Itoh

  • 0
    TI__Genius 16030 points

    Hello Itoh,

    Can you please confirm that "rmii tx clock shift" of register 0x0017 and "rmii receive clock" of register 0x000A is in accordance with MAC side's requirements?

    I also see RMII underflow detection. I am discussing it with team here and will get back to you.

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    TI__Genius 11320 points

    Hello Vikram-san,

    My customer is checking the MAC side's requirement.

    Could you please update the discussion results?

    Also, could you please explain what RMII underflow detection stand for?

    One more question, is it OK to leave bootstrap pins open when configuring RMII master mode?

    Regards,

    Itoh

  • 0 in reply to Kazuki Itoh
    TI__Genius 16030 points

    Hello Itoh,

    Is the issue resolved? Did they find something from the MAC side?

    I recevied following feedback from design team :

    1. Could not find any issue in the configuration based on register logs.

    2. What is the result of analog loopback? It is TBC in the xls.

    3. Can you confirm if the issue is with RMII TXD[1:0] being garbled and you also see incorrect packets received by link-partner (PC)?

    --

    Regards,

    Vikram