• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 34 subscribers
  • Views 764 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DP159: HDMI output may not be performed with APPLY_RXTX_CHANGES setting

Masahiro Koyama
Prodigy 80 points

Part Number: SN65DP159

It may not be output at startup or when changing the mode setting (APPLY_RXTX_CHANGES). If it is not output, it will be output by repeating
APPLY_RXTX_CHANGES, but if APPLY_RXTX_CHANGES is set during output, it may not be output frequently.

The operating environment is as follows.
1) The circuit diagram is attached.
2) The input to DP159 is the HDMI IP output of Xilinx.
3) The VCC / VDD / OE power-up sequence complies with the regulations.
4) The tested images are 1080P59.94 and 2160P59.94, both of which occur.
5) The register value of bank 1 differs depending on whether it is output or not (attached).
6) Reflecting the settings in PD_EN is less frequent than APPLY_RXTX_CHANGES, but it does not solve the problem.

It would be helpful if you could give me some advice.


By the way, if I can check the output status with the hidden register of DP159, I can set APPLY_RXTX_CHANGES while checking the flag. Is there such a flag?

2160P output (normal register read value):
   DP159 register dump [BANK:00]
        ADDR[00] = 44 50 31 35 39 20 20 20 01 06 33 9A 49 00 00 0F
        ADDR[10] = 00 00 00 00 00 80 00 20 00 00 00 00 85 0D 00 00
        ADDR[20] = 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[30] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[40] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[50] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[60] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[70] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[80] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[90] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[A0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[B0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[C0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[D0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[E0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[F0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

   DP159 register dump [BANK:01]
        ADDR[00] = C3 01 3F 00 A0 00 00 00 01 00 00 33 00 00 11 00
        ADDR[10] = 0F 30 20 07 01 00 00 00 00 00 00 00 00 00 00 00
        ADDR[20] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[30] = 07 30 08 00 00 00 00 00 00 08 00 08 04 06 00 00
        ADDR[40] = 80 80 80 80 C1 00 00 00 FE 3F 7F FF 03 00 21 71
        ADDR[50] = 00 00 00 00 00 00 00 00 00 00 00 00 40 40 40 40
        ADDR[60] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[70] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[80] = 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[90] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[A0] = 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[B0] = 5E 82 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[C0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[D0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[E0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[F0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01

2160P output (register read value at abnormal time)
　　DP159 register dump [BANK:00]
        ADDR[00] = 44 50 31 35 39 20 20 20 01 06 33 9A 49 00 00 0F
        ADDR[10] = 00 00 00 00 00 80 00 20 00 00 00 00 85 0D 00 00
        ADDR[20] = 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[30] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[40] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[50] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[60] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[70] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[80] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[90] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[A0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[B0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[C0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[D0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[E0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[F0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

　　DP159 register dump [BANK:01]
        ADDR[00] = C3 01 3F 00 A0 00 00 00 01 00 00 33 00 00 11 00
        ADDR[10] = 0F 30 20 07 01 00 00 00 00 00 00 00 00 00 00 00
        ADDR[20] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[30] = 07 30 08 00 00 00 00 00 00 08 00 08 04 06 00 00
        ADDR[40] = 80 80 80 80 C1 00 00 00 F8 3F 7F FF 03 00 21 71
        ADDR[50] = 00 00 00 00 00 00 00 00 00 00 00 00 40 40 40 40
        ADDR[60] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[70] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[80] = 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[90] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[A0] = 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[B0] = 5E 82 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[C0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[D0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[E0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
        ADDR[F0] = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01

  • 0
    Prodigy 80 points

    Additional information.

    This issue seems to occur with Sinks that support HDMI-2.0.
    After checking the HDMI standard, I found that the HDMI-2.0 compatible Sink has an SCDC status register to
    notify the Sink status, so it may be possible to take a workaround.
    However, I don't understand why this happens.

    If I continue to set APPLY_RXTX_CHANGES while the FPGA continues to output the 2160P signal to the DP159,
    the image may or may not be displayed. In this case Lane1 wasn't always locked.

     　No output case(read back sink's scdc register):
    　　　HDMI TX: SCDC 0x01: 1
         HDMI TX: SCDC 0x20: 3
    　　　HDMI TX: SCDC 0x21: 0
    　　　    HDMI TX: SCDC 0x40: B

         Normal case(read back sink's scdc register):
         HDMI TX: SCDC 0x01: 1
         HDMI TX: SCDC 0x20: 3
         HDMI TX: SCDC 0x21: 1
         HDMI TX: SCDC 0x40: F

  • 0 in reply to Masahiro Koyama
    TI__Guru**** 185641 points

    Hi,

    Per the HDMI2.0, whenever the source changes the TMDS_BIt_Clock_Ratio bit between 0 and 1, the source (FPGA) needs to follow the following procedure:

    1. The source suspends its data and clock output

    2. Write to the TMDS_Bit_Clock_Ratio bit to change from 1 to 0 or 0 to 1

    3. Wait min of 1ms and max of 100ms from the time the TMDS_Bit_Clock_Ratio bit is written until resuming transmission of the data and clock output. 

    4. Source may read the state of the Clock_Detected status via the SCDC to verify the sink is detecting the TMDS clock.

    When you are changing the resolution, are you disabling the FPGA output?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 80 points

    Hi David

    　Thank you for your reply.

    　I did not observe it directly on the oscilloscope, but I think that the procedure is taken from the indirect results.
    This is because it is basically a procedure described in the HDMI 2.0 standard, and it is not a special one.
    　Also, I don't think it applies to HDMI-1.4 (1080P59.94).

    　

  • 0 in reply to Masahiro Koyama
    TI__Guru**** 185641 points

    Hi,

    For HDMI1.4, the TMDS_BIt_Clock_Ratio bit is 0 (1/10). For HDMI2.0, the TMDS_Bit_Clock_Ratio is 1 (1/40). The DP159 snoops the DDC bus between the source and the sink and set its TMDS_CLOCK_RATIO_STATUS bit base on the TMDS_Bit_Clock_Ratio bit.

    The problem here is the clock / data are already detected and running before the TMDS_CLOCK_RATIO bit gets set to enable 1/40 mode. In this case, the DP159 will try to adjust to a 1/40 ratio by slowing down the clock instead of keeping the clock rate the same and increasing the data rate. And this problem can be resolved by causing the receiver clock detect to restart (using HPD_SNK, apply_rxtx_change, etc). But you don't need to continue toggling HPD_SNK or  apply_rxtx_change.

    But you have to make sure the FPGA follows the HDMI spec and turns off its data and clock output when transition between the HDMI1.4 and 2.0.

    Thanks

    David

     

  • 0 in reply to David (ASIC) Liu
    Prodigy 80 points

    I suspect the problem wouldn't have occurred if the DP159 had a fixed Clock ratio mode.

    I was able to work around this issue by repeatedly manipulating DP_EN while checking the
    status register of the SCDC (less trials than APPLY_RXTX_CHANGES).