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SN65DPHY440SS Doesn't work

Justin Jang
Prodigy 20 points


We confirmed that a normal signal appeared at the front end of the Retimer, but only the LP signal came out at the rear end, but the HS did not come out.

So, we found a similar phenomenon in the forum and set the following through IIC and confirmed that HS appeared.

Write Register 0x50 with 8’h1f //Override enable for HS TX path
Write Register 0x51 with 8’h1f //HS TX path enabled.
Write Register 0x61 with 8’h1f  // Disable LP path.
Write Register 0x70 with 8’h1f  //Override enable for HS RX path
Write Register 0x71 with 8’h1f  // HS RX path enabled.
However, the LP signal could not came out. Inquire about the register setting or method that allows both LP and HS to come out
  • 0
    TI__Guru**** 182761 points

    Hi,

    Are you seeing this issue on lane0? DPHY440’s LP TX is expecting to connect to an unterminated LP RX.  With Lane 0 path (DA0P/N and DB0P/N) supporting bi-directional LP signaling, it is very important that DB0P/N LP TX is connected to an unterminated LP RX. Otherwise the DPHY440 can't transition from LP to HS.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Hi,

    This problem can be seen in all lanes.I confirmed what you said. The signal was normal.
    And the clock signal was a continuous signal. Does the continuous clock signal affect the operation?
  • 0 in reply to Justin Jang
    TI__Guru**** 182761 points

    Hi,

    The clock and data lanes can be independent from each other. You can have the clock lane in the continuous mode while the data lane is in LP/HS mode.

    Since the clock is in continuous mode and does not support LP, you need to place the clock lane in HS mode only. The following commands will place only the clock lane in HS mode.

    (Address, Data)

    (0x50, 0x10), // HS TX path Override enable
    (0x51, 0x10), // HS TS path enable
    (0x61, 0x0F), // Disable LP path.
    (0x70, 0x10), // HS RS path Override enable
    (0x71, 0x10) // HS RX path enable​

    On the data lane, you have to make sure it is transitioning correctly from LP to HS by following LP11, LP01, LP00, and then HS data.

    Thanks

    David