DP83867IR: DP83867IR : In MII/RGMII 100Mbps Tx communication not working

Hello Charchil,

Can you please share the schematic again as attachment is not loading. May be you can try attaching pdf.

Also just to be sure that I understood your issue, can you please confirm the following:

1. there is no data on TX_* pins of the PHY (which is driven by MAC) ?

 2. You are using 100mbps mode for even during Rgmii usecase?

3. RX_* pins and final data going from these pins to MAC is getting captured by MAC correctly?

If answer to all of the above is yes, then your Rx_clk_delay is good already and hence do not change it. Only change tx_clk_delay to 2ns. Above register settings show that you are changing both together.

Reading register 32 shows that you are in Rgmii mode when you want to be in Rgmii mode. If you are using straps to enter Rgmii mode then you may also verify it by reading register 0x006E.

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Regards,

Vikram

Hello Vikram,

Thank you for your quick response.

PFA pdf for schematics./cfs-file/__key/communityserver-discussions-components-files/138/Ethernet123.pdf

1. there is no data on TX_* pins of the PHY (which is driven by MAC) ? -> Yes, No data observed on TX_D* lines.

 2. You are using 100mbps mode for even during Rgmii usecase? -> Yes, 100Mbps is used for RGMII use case. 

3. RX_* pins and final data going from these pins to MAC is getting captured by MAC correctly? - Yes, Data is being received by MAC and Eth stack in both MII & RGMII modes.

"Only change tx_clk_delay to 2ns. " -> I did try this delay with 4ns, 2ns & 0ns but in all 3 cases tx is not observed.

"Above register settings show that you are changing both together." -> Do you mean both Rx_Delay & Tx_Delay needs to be update with separate write call to PHY? 

Further I want to know how to confirm PHY is operating in MII mode?

Thank you in advnace.

Best Regards,

Charchil Dudani

Hello Charchil,

If TX data is not toggling and RX data is fine, then you may have to check some setting in the MAC. When Rgmii is not enabled (register 0x032)...mii is enabled. You may confirm the same by the clock frequency on Rx_clk.

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Regards,

Vikram

Hello Vikram,

Thank you for your reply. I see that MII & RGMII modes are set properly. 

I observed in the MAC that request communication mode is FD but as per status register it is Half Duplex. Where as PHY is set & operating in FD.

Does this mismatch of MAC(HD) & PHY(FD) create any issue for Tx communication?

Thank you,

Best regards,

Charchil 

Hello Charchil,

Did you try making MAC (FD)? Which register did you check for PHY'S FD status?

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Regards,

Vikram

Hi Vikram,

I am setting BMCR (0x0000) bit 8 to 1 which enables FD mode.

I am reading BMSR (0x0001) bit 14 as 1 which says device is capable of 100Base-Tx FD capable.

PHY STATUS REG (0x0011) bit 13 is set to 1 as well.  (Auto neotiation is disabled)

Is this correct for confirm FD mode of PHY?

Another query is: In MII mode Tx_CLK is provided from PHY to MAC and for 100Mbps speed TX_CLK shall have 25Mhz freq. Do I need to make settings in PHY for 25Mhz ? Or will it be set automatically. 

GTX_CLK will not be used in MII, Could you confirm once?

Thank you,

Best regards,

Charchil

Hello Vikram,

Thank you for your support so far. 

MII/RGMII TX communication is also working fine now.

Could you confirm that DP83867IR doesn't support RMII mode?

After this you can close this ticket.

BR,

Charchil Dudani