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TLK10031: TLK10031 Without software provision to be used

guru sai
Intellectual 530 points
Part Number: TLK10031

Hi, as per our requirement, we want to use the Transciever TLK10031 without software provision? can we can able to handle via hardware alone? if any design document, please share us

  • 0
    TI__Guru* 91440 points

    Greetings Sal,

    It is highly recommended to use MDIO interface to fine tune or setup the registers in different test modes. This could come in handy during board bring up.

    Regards,, Nasser

  • 0 in reply to Nasser Mohammadi
    Intellectual 530 points

    Hi nasser

    Thanks for the reply.

    What should be the frequency of input reference clock?

    And as per our application, we shall use 3 no of tlk10031 (one is master and another two are slaves).

    The low side signals are connecting via mux, so that master can be connected to either of slaves.

    While connecting to mux should be connect the reference clock out also?

    What is the impact / use of reference clock out?

  • 0 in reply to guru sai
    TI__Mastermind 19155 points

    Hi,

    The REF_CLK frequency depends on desired data rate. Please refer to the product datasheet. Below is example for 10G-KR and SFI.

    Table 7-1. Specific Line Rate and Reference Clock Selection for the 10GBASE-KR Mode:

    LOW SPEED SIDE

    HIGH SPEED SIDE

    Line Rate

    (Mbps)

    SERDES PLL Multiplier

    Rate

    REFCLKP/N (MHz)

    Line Rate

    (Mbps)

    SERDES PLL Multiplier

    Rate

    REFCLKP/N (MHz)

    3125

    10

    Full

    156.25

    10312.5

    16.5

    Full

    156.25

    3125

    5

    Full

    312.5

    10312.5

    8.25

    Full

    312.5

    Are you planning on using the recovered clock output? If not you may pull to GND via 50ohm. See below from datasheet.

    Channel Output Clock. By default, this outputs is enabled, and outputs the high speed side recovered byte clock (high speed line rate divided by 16 or 20). Optionally, they can be configured to output the VCO clock divided by 2. (Note: for full rates, VCO/2 pre- divided clocks will be equivalent to the line rate divided by 8; for sub-rates, VCO/2 pre- divided clocks will be equivalent to the line rate divided by 4). These CML outputs must be AC coupled.

    During device reset (RESET_N asserted low), pin-based power down (PDTRXA_N asserted low), or register-based power down, these pins are floating.

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Intellectual 530 points

    Hi Rodrigo Natal,

    Thanks for the reply.

    Can you please suggest the Oscillator for Reference clock input?

  • 0 in reply to guru sai
    TI__Mastermind 19155 points

    Hi,

    TI has a lot of oscillator options in our portfolio. See below link for one example.

    www.ti.com/.../LMK61E2