SN65DP159: HDMI 2.0 SI measurement fail

Hi,

What resolution are you using for the HDMI2.0 compliance testing?

Are you using pin-strap mode or I2C mode? Please read the DP159 register 0x0B and make sure the TX_TERM is set to 75-150ohm and TMDS_CLOCK_RATIO_STATUS is set to 1 for HDMI2.0.

If the TX_TERM and TMDS_CLOCK_RATIO_STATUS are set correctly, please toggle the HPD_SNK next (High-Low-High) next.

Thanks
David 

Hi David:

     I use pin-strap mode, and the TX_TERM is set Auto, so I need change it to pull down 64.9K ohm to GND?

I don't know how to check TMDS_CLOCK_RATIO_STATUS is set to 1 or not. Which pin in pin-trap mode is for TMDS_CLOCK_RATIO_STATUS?

Thank you.

Hi,

What is the resolution you are using for the HDMI compliance test?

You need to use the I2C to read register 0x0B to check the TMDS_CLOCK_RATIO_STATUS bit. If the TMDS_CLOCK_RATIO_STATUS is set correctly, then the TX_TERM will also set correctly. Just forcing the TX_TERM to GND will not fix the clock frequency issue.

Thanks

David

Hi David:

     I use Intel RKL-S QS CPU to verify this issue again. But the TBit rate still wrong. I set the resolution to 3840 x 2160 at 60Hz and the link is done. But when I try to switch the resolution setting, the waveform will not be changed. I guess the EDID communication is something wrong. Would you please teach me how to check the register 0x0B? If I use RW, how to check it? Or any tool could be used in Win10 ? Thank you. 

Hi,

The DP159 registers are accessed through the SCL_CTL and the SAD_CTL pins. In the pin-strap mode (I2C_EN pin = 0), the registers are read-only. In the I2C-mode (I2C_EN = 1), the registers are read/write. You can use a standard I2C controller to access the registers. 

In the I2C-mode, please refer to this app note on the registers configuration: 

The I2C address is set by A0 and A1 as shown in the table below. Depending on the pullup/pulldown on A0 and A1, the address can be 0x5E, 0x5D, 0x5C, or 0x5B.

Per the HDMI spec, when source changes between HDMI1.4 and 2.0, 

•         The source shall suspend the transmission of the TMDS clock and data.

•         Change the TMDS_CLK_RATIO_STATUS bit -> The DP159 will snoop the DDC bus between the source and the sink and set the TMDS_CLK_RATIO_STATUS bit based on the DDC snooped value. 

•         Allow min of 1ms and max of 100ms before resuming transmission of TMDS clock and data

When you set the resolution to 3840x2160 at 60Hz and then toggle HDP_SNK multiple times, are you then able to see the correct clock frequency output?

Thanks

David

Hi David:

     I found one thing when I do the HDMI 2.0 test. That is when I set 3840x2160 at 60Hz, ready to do HDMI 2.0 test. If I change the resolution of the HDMI port,

the waveform shows on scope will never change. Does it mean the EDID communication is not work anymore? Thank you.

Hi,

When you change the resolution, could you toggle the HPD and see if the waveform changes?

Thanks
David

Hi David:

    Yes, we also try toggle HPD to make waveform change, but it doesn't work. It seems Intel VGA driver or firmware doesn't set register 0x0B? Thank you.