SN65DSI86-Q1: MIPI to eDP latency

Hi,

We don't have a spec on the latency. Since the DSI86 will buffer a full video line before starting the DP transmission, you will expect the latency of at least one full video line.

Thanks
David 

Hi David

Could you help clarify the meaing of "one full video line"?

My understanding is, take a WQXGA/60HZ LCD as an example,

for landscape mode(2560RGB*1600), it should be 1/60/1600=10.4us

for portrail mode(1600RGB*2560), it should be 1/60/2560=6.5us

Is that correct?

I also find some recommends in the spec as below, expect that ,any other suggestion about how to make the latency as short as poosible?

"As required in the DSI specification, the v requires that pixel stream packets contain an integer number of pixels
(that is, end on a pixel boundary); TI recommends to transmit an entire scan line on one pixel stream packet.
When a scan line is broken in to multiple packets, inter-packet latency must be considered such that the video
pipeline (that is, pixel queue or partial line buffer) does not run empty (that is, under-run); during scan line
processing. If the pixel queue runs empty, the SN65DSI86 transmits zero data (18’b0 or 24’b0) on the
DisplayPort interface"