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TS3DV642: Layout confirmation

Part Number: TS3DV642

 Hi

My customer uses TS3DV642 design and encounters problems, please help confirm.
Questions are as follows:


1. Intel PDG requires the capacitance of the DP signal to be close to the connector end (within 984mils)
However, the TS3DV642 datasheet requires the aux capacitor to be placed on the left side of the chip.
This part is a bit difficult on layou. Can I change the capacitor to the right side of the switch?

2. If there are 2 pairs of data unused in the end device of TS3DV642, can directly NC?

  • Hi,

    1. Intel PDG requires the capacitance of the DP signal to be close to the connector end (within 984mils)
    However, the TS3DV642 datasheet requires the aux capacitor to be placed on the left side of the chip.
    This part is a bit difficult on layou. Can I change the capacitor to the right side of the switch?

    Yes, you can do this. What is being connected on the other port? Since the caps are placed on the right side of the switch, this means the other port AUX is also getting AC coupled.

    2. If there are 2 pairs of data unused in the end device of TS3DV642, can directly NC?

    Please leave both the unused lane input and output NC.

    Thanks

    David

  • Hi David

                Sorry, I cannot leave both the input & output.

                   The request as below:

                   Source(DP) to device A & B, device A use D0~D3

                                                            device B use D0~D1

                   Leave output B(D2,D3) > ok ?

  • Hi,

    If this is the case, I would recommend having 1k pulldown on the two unused output.

    Thanks

    David