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DP83848-EP: DP83848-EP

Part Number: DP83848-EP

Having similar issue as others where upon power up the ethernet phy is unable to establish a link. Cycling the power seems to cause the chip to work or not about 50% of the time. We are using hardware strapping to setup the device. Sounds like same issue as "DP83848-EP: PHY Component Intermittently Powering up in Bad SSD Mode" but did not see a solution for the issue. Any help would be appreciated.

  • Hi Matthew,

    Can you let me know if any of the following steps resolve the problem:

    1. Issue a hardware reset through register 0x001F=8000 or toggling RESET_N
    2. Issue a software restart through register 0x001F=4000
    3. Plug out and plug in ethernet cable

    Please also share the schematic and register information for register 0x00-0x1F in a good and bad power-up. I'd like to know if you also use an FPGA or a dedicated MAC with the PHY. One troubleshooting steps would be to verify the bootstrap voltage on each strap pin to ensure the device is booting into the correct mode. An internal pull-up or pull-down resistor on a MAC/FPGA pin could interfere with the boot settings of the PHY.

    Regards,
    Justin