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TUSB564: how to save TUSB564 power consumption if PC is in sleep mode?

Frank(EP) Liu
Expert 4780 points
Part Number: TUSB564
Other Parts Discussed in Thread: TPS65987

hi Sir,

my customer application is DP UFP device(no usb3) with battery. when PC is in sleep mode, TUSB564 still works with full power. there is AUX snoop feature for power saving. due to the note in datasheet below, they don't know if they can enable this feature or not.

When TUSB564’s AUX snoop feature is enabled, the syncs defined by the DisplayPort
standard must be received in order for AUX snoop feature to function properly. AUX writes
to panel’s DPCD address 0x00600 and 0x00101 should result in SET_POWER_STATE
and LANE_COUNT_SET fields at TUSB564’s offset 0x12 to get set to the appropriate
value. If these fields do not get set correctly, then incoming AUX may not be compliant. If
this is the case, then it is best to disable AUX snoop by setting the
AUX_SNOOP_DISABLE field at offset 0x13.

any information to help customer to do the risk assessment if they enable the AUX snoop feature?

any other suggest to help the TUSB564 power saving when external DP source is in sleep mode?

BR,

frank

  • 0
    TI__Guru 64326 points

    Hi Frank,

    For TUSB564 AUX snooping is enabled by default but can be disabled by changing AUX_SNOOP_DISABLE. Does the scaler or PD controller change this setting through I2C?

  • 0
    TI__Guru**** 176371 points

    Frank

    In the GPIO mode, you can choose to have both the CTL0 and CTL1 pins driven low to achieve shutdown mode.

    In the I2C mode, you can also choose to have both the CTL0 and CTL1 bits set to 0, or disable AUX snooping and then manually disable each DP lane to achieve low power state.

    If AUX snoop is enabled, the power down state is achieved automatically based on the snooping of the AUX bus between the source and the sink.

    Thanks

    David

  • 0 in reply to Malik Barton57
    TI__Expert 4780 points

    Malik,

    PC here means external DP source in case you feel confused. 

    yes, we know how to enable and disable the snoop mode. from the note in datasheet, my customer feels risky to enable snoop mode. any information to help assessment of compatibility issue for snoop mode?

    BR,

    frank

  • 0 in reply to David (ASIC) Liu
    TI__Expert 4780 points

    David,

    understood that. we use i2c mode. Just we don't know when PC goes to sleep mode. so, we cannot disable DP manually. any other method to save the power?

    How does everyone handle the power consumption condition? always using full power mode?

    BR,

    frank

  • 0 in reply to Frank(EP) Liu
    TI__Guru**** 176371 points

    Frank

    If the Scalar is the I2C primary that controls the TUSB564. The Scalar will know the PC has went into the sleep mode through the AUX communication and then the Scalar can program the TUSB564 into low power mode through the I2C bus.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Expert 4780 points

    hi David,

    TUSB564 is controlled by TPS65987 i2c event. can scalar control TUSB564 through i2c to TPS65987?

    When TUSB564 is into low power mode, AUX bus is off, right? How can scalar know when PC is awake?

    BR,

    frank

  • 0 in reply to Frank(EP) Liu
    TI__Guru**** 176371 points

    Frank

    You can put the Scalar, the TPS65987 and the TUSB564 on the same I2C bus. But in this case, the Scalar must be the I2C primary and the TPS65987 and the TSB564 must be the I2C secondary.

    My proposal is to disable the DP lanes only, but still keep the AUX/SBU switch active. So the Scalar can re-enable the lanes when the PC wakes up and starts the DPCD communication on the AUX bus again.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Expert 4780 points

    hi David,

            To consider of DP flow, I worry about the sequence about LANE, and AUX.

            When PC wake, it will start to handshake with monitor via AUX, so the flow should:

    1. PC wake up and start AUX communication.
    2. Scaler enable DP lane via I2C
    3. PC start DP link training via AUX and DP lane

    If source is quickly than our response, than step3 will early then step 2.

    It may cause compatibility issue, am I right?

    BR,

    frank

  • 0 in reply to Frank(EP) Liu
    TI__Guru**** 176371 points

    Frank

    Between step 2 and 3, the Scalar can hold off from asserting the HPD until the I2C configuration is completed and then drive the HPD high. The source will not start the link training until it sees the HPD from the sink side being high.

    Thanks

    David