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Original question:

DS90UB948-Q1: ub948 output voltage setting -VOD

DS90UB948-Q1: link error enable -- UNLOCK

James Zhan
Expert 4365 points
Part Number: DS90UB948-Q1
Other Parts Discussed in Thread: ALP

Hi team,

My customer is using UB948 and enable the link error count by setting 0x49=0x1F in their initialization.

Then they enter the pattern mode with internal clk and internal timing. after exiting the pattern mode they found LOCK pin unlock.

If they didn't enable the link error count in the first place(0x49=0x03), then nothing wrong when entering and exiting the pattern mode.

Could you help to share your advice for this ?

Thanks.

  • 0
    TI__Mastermind 37370 points

    Hi James,

    What is the serializer side 947? Did you enable the patgen on 947 or 948 side? The lock indicator is only showed when you have for example 947 connect to 948 where it established the linked and locked.

    Aaron

  • 0 in reply to Aaron Heng
    TI__Expert 4365 points

    Hi Aaron,

    Ser is 947. But they enable the pattern mode(internal clk+ internal timing) with local MCU I2C bus.

    Do we expect any similar kind of behavior after enabling link error count then entering the patter mode?

    I've asked customer to try disable the link error count before enabling the pattern mode, then everything is okay.

    Could you help to provide some advice for this?

    Thanks.

  • 0 in reply to James Zhan
    TI__Mastermind 37370 points

    Hi James,

    If you encountered link error, it might be an issue with poor SI performance. Are they using TIEVM or their board? If they are using their board, you might want to tap on the 948 I2C and run Margin Analysis Tool in ALP.

    Aaron

  • 0 in reply to Aaron Heng
    TI__Expert 4365 points

    Hi Aaron,

    They're using their own board, not TI EVM board.

    I've asked customer to run the MAP for link SI performance and will share to you later. But I think the SI should be okay since they only having this issue while in pattern mode.

    Could you help to try to reproduce on TI EVM board? I am out of office and didn't have the EVM in hand.

    It seems very weird that they have four different production project(different schematic/layout) having similar issue.

    I am suspecting the link error count adds up when the enabling the pattern mode(internal clk) because the clk change from the serial FPDlink to the internal pattern reference clk.

    Could you help to share more advice for this? Customer is pushing for the answers, thanks.

    James

  • 0 in reply to James Zhan
    TI__Mastermind 37370 points

    Hi James,

    I know your frustration, but we need to go through step-by-step. May I ask why you need to write 0x49 = 0x1F? The 0x49[4:2] are reserved bits. These bits are for internally use only.

    Aaron

  • 0 in reply to Aaron Heng
    TI__Expert 4365 points

    Hi Aaron,

    Sorry for the typo. I mean setting the 0x41=0x03 and 0x41=0x1f for the link error count enabling.

    Could you share more details about this case?

    Thanks.

  • 0 in reply to James Zhan
    TI__Mastermind 37370 points

    Hi James,

    Let have a discussion offline since you reached out to me.

    Aaron