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XIO2001: D8h register settings for XIO2001

Leo Chow
Expert 3120 points
Part Number: XIO2001

Hi,

I'm planning to operate device in external clock mode & I'm planning to add EEPROM for XIO2001 application. Can I know where can I locate the default values to program the EEPROM? FYI, I would like to change register at offset D8h.

Since I’m using external clock source to XIO2001 CLK (F03) and to other devices, should I set the CLKRUN_EN = low and GPIO0 = not connected? Do I need to disable CLKOUT0 to CLKOUT6 at offset D8h and how XIO knows it has to use external PCI clock source?

Assuming XIO2001 is using CLK (F03) pin to sync the PCI data with devices, it doesn’t matter if using internal or external clock source since internal clock source also connected to CLK pin (through CLKOUT6)?

Regards,

Leo

  • 0
    TI__Guru* 93670 points

    Hi Leo,

    Please attached note default EEPROM that is used with the EVM.

    For clock frequencies other than 33MHz and 66MHz (for instance 50MHz), an external oscillator is required. When an external PCI bus clock source is selected, the external clock source is connected to the PCI bus clock input (CLK). For external clock mode, all seven CLKOUT6:0 terminals must be disabled using the clock control register at offset D8h.

    Regards,, Nasserhttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/8240104C.WR3