Hi , In the data sheet revised 2019 on page 20 it is said:
(2) An attached MAC should drive the transmit signals using the positive edge of TX_CLK. As shown below, the MII signals are sampled on
the falling edge of TX_CLK.
pointing to fig 10 which shows sampling of data on rising edge of the clock. Coul dyou please clarify if this is an error in ds and what is teh sampling edge of the chip.
