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TMDS181: PLL divisor 1/160 instead of 1/40

Andre Salehi
Prodigy 30 points
Part Number: TMDS181

Hello,

 I’m having a problem with the TMDS181.   My problem is very similar to these three threads:

Unfortunately, the thread goes offline (direct email) and I don’t know what was the solution. 

Block diagram shows my Use Case:

We are seeing an issue with the TMDS181 as a sink device where it does not pass through the clock properly after hotplug of Panasonic 4K camera 3480x2160p60 (YU422 10bit).

 We can scope the clock going to the IN_CLKp/n pins is 148.5 MHz, but the clock coming out of OUT_CLKp/n is 37.125 MHz.

I have confirmed Camera sends expected Character Rate (0xA8, 0x20,0x3) and TMDS181 registers 0x0B = 0x02

My question, what is the root cause for OUT_CLK = 37.125MHz?

  • 0
    TI__Guru**** 177301 points

    Hi,

    If you toggle the HPD_SNK or the PD_EN bit, are you then able to see the CLK_OUT to be the correct frequency?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 30 points

    Hi David,

    I toggled HPD_SNK and TMDS181 outputted the correct frequency.  Thank you!!

    I am curious, why was the device outputting 37.125MHz to begin with?

    Best regards,

    Andre  

  • 0 in reply to Andre Salehi
    TI__Guru**** 177301 points

    Andre

    When a source switches between HDMI1.4 and 2.0, per the HDMI spec

    1. The source needs to stop the transmission of the data and clock

    2. The source communicates the change (TMDS_CLOCK_RATIO_STATUS = 0 for HDMI1.4 and 1 for HDMI2.0) to the sink. The TMDS181 will snoop the DDC bus and set its TMDS_CLOCK_RATIO_STATUS bit accordingly.

    3. The source needs to wait minimum of 1ms and maximum of 100ms before re-starting the transmission of the data and clock.

    The issue is that some sources are not HDMI spec compliant and will change between the HDMI1.4 and 2.0 on the fly without stopping the transmission of data and clock. But the TMDS181 RX CDR is locked at the HDMI1.4 or 2.0 and can't adapt to the change on the fly. By toggling the HPD_SNK, we are forcing the TMDS181 RX CDR to re-lock to the new data/clock and then the TMDS181 will work properly.

    Thanks

    David