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DP83867CR: Configuration, straps, design and layout information

Ioannis Aspiotis
Prodigy 50 points
Part Number: DP83867CR
Other Parts Discussed in Thread: TIDA-00204

Hello,

We are using a custom setup with a SOM (with AM335x) and a base board where we wanted to migrate to a new PHY (from AR8035-AL1A  to DP83867CRRGZ). So here are my questions:

  1. On page 48 of the datasheet for Autoneg Disable function is says that “Straps Required” for RX_DV/RX_CTRL or if not possible a certain bit must be cleared in Configuration Register 4. We have no strap placed in our initial design so is it possible to clear that bit from U-boot. In case none of the two actions are taken, would you consider that as a show-stopper for the device to work?
  2. Unfortunately some signals where swapped by mistake in the RGMII interface (Rx_CTL with Rx_CLK and Rx_D0 with Rx_D1) so we are thinking to place some mod wires just to verify a basic functionality before going to a new revision of the base board. I understand that this will ruin impedance and length matching, but do think there is chance to work even in lower speeds just to verify basic functionality or there is no point in doing that mod?
  3. About RGMII interface, how strict should the length matching be within the Rx and Tx busses? I’ve seen that TIDA-00204 ref design uses 0.254mm. I understand that the more tightly match the better but if there is a more loose matching of about 4-5mm would you think it would still be ok?
  4. We’ve noticed that in TIDA-00204 there are 4.7pF caps to ground for the MDI lines. Are these necessary or they can be omitted?
  5. If VDDA1P8 is not used, does it still need a decoupling cap or we should leave it floating?

Thank you in advance.

  • 0
    TI__Genius 16030 points

    Hello,

    Please find following answers in the same order as questions :

    1. Yes, please do write the bit if the strap is not possible.

    2. You should try mod wiring anyways. For gigabit operation : skew between rgmii data signals and clock should be less than 200ps (tight) and that may become marginal with jumper wires. But if you are using 100mbps operation then their is higher chance that it will work with jumper wires also.

    3. Consider this 200ps max delay mismatch number while designing RGMII interface. Controlling this delay further to 50ps or 100ps will give both MAC and PHY more margins for any other signal integrity deviations.

    4. They can be omitted. They are usually the placeholders for passing electrical compliance test with different RJ45 connectors.

    5. Must leave it floating.

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    Prodigy 50 points

    Thank you very much Vicram.

    About the skew, just to be sure I understood correctly, the values you mention should be followed not only between rgmii data signals and clock but also within the rgmii data signals themselves (e.g. Rx_CTL to RxD0 to RxD1 e.t.c. ) correct or they need to be tighter? I am asking because the datasheet (page122) states that "Skew between TXD[3:0] lines should be less than 11 ps, which correlates to 60 mil for standard FR4".

    What about the skew between Tx and Rx lanes? I understand that it is not that important but do you have a recomendation for that as well?

    So if my calculations are correct, with travel speeds of about 150mm/nsec for FR4, the timings you mention would correspond to approximately: 30mm for the 200ps (tight), 15mm for 100ps and 7.5mm for 50ps.

    So since the length matching in our situation is less than 10mm, this may give us a chance to use the jumper wires if we can keep them short enough.

    Thanks again,

    Giannis