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PCA9306: Rise time for PCA9306

Mayank Mishra
Intellectual 780 points
Part Number: PCA9306

Hi Team,

My customer is facing below issue with this device

They observed that in and out of PCA9306  shows rise time of 3us and 250ns respectively.

And pullups used are 4.75k and 0.47k. so they changed the pullup value for at input side to 2k and with this rise time reduced to 700ns and also with this change rise time of output changed to 170ns.

So they want to understand if this is the expected behavior or change in pullup at in and out should not affect each other.

Attached are the waveforms they have captured

PEX.zip

  • 0
    Guru 316940 points

    This device is a passive switch. At voltages between 0 V and VREF1, the switch is closed, and the two pins are connected with a certain resistance (which implies that both pull-up resistors work in parallel). At higher voltages, the switch is open, and the other pin's voltage is determined only by its pull-up resistor.

    Also see [FAQ] How do the LSF translators work?

  • 0 in reply to Clemens Ladisch
    TI__Intellectual 780 points

    Hi Team,

    Further to the above reply, please refer below query from customer:

    two questions regarding PAC9306

      1. Changing the pullup resister value at input side  (Side A 3.3v ) does it have any impact on rise time of output signal (Side B  1.8v) or vice versa?
      1. If yes, please check the attached waveforms ,and confirm the whether these are correct or not (please suggest if any changes to be done).

     

    Note: I2C operating at 100KHz.

    0513.WAVEFORMS.zip

  • 0 in reply to Mayank Mishra
    TI__Guru 73181 points

    Hi Mayank,

    A) Technically yes since the pass FET will act as a short between side 1 and side 2 until the gate to source voltage exceeds Vg-Vth. After which the two sides are treated as as separate. The actual timing differences during the 'closed/short' of the pass FET is probably low double digit nanoseconds when you compare different pull up values. The bigger affect you will see is the VoL will shift higher with lower pull ups since you treat the two pull ups as parallel resistors when the pass FET is in the linear region of operation resulting in higher IoL to the external driver.

    B) For I2C/SMBus, the max allowed rise time for a 100kHz frequency or less is 1000ns measured from 70% to 30%. I would suggest just checking the waveforms on the worst case pull ups and verify the signals look compliant to that.

    -Bobby