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DP83822IF: DP83822IF

Sebastien Chapeau
Intellectual 290 points
Part Number: DP83822IF


Hi

I’m trying to setup FREE RTOS + TCP on a custom board using xilinx ultrascale + TI DP83822 PHY.
The PHY as no boot strap as the HW team intended it to be configured by SW.

The PHY wiring on the board is meant to use RGMII interface.

I can't get any traffic on Ethernet but most puzzling is that the PC the board is attached to indicates cable is disconnected.

To my understanding even without any transmit form the MAC the PC should at least recognize a cable is connected if initialization is OK.

I've done the following initialization for the PHY :

#define PHY_TI_BMCCR 0x00 // Basic Control Mode register
#define PHY_TI_BMCCR_RESET_MASK 0x8000
#define PHY_MODEL_TI_DP83822_AUTONEGO_EN 0x1000
#define PHY_MODEL_TI_DP83822_AUTONEGO_RESTART 0x0200

#define PHY_TI_PHYRCR 0x1F // PHY reset control register
#define PHY_TI_PHYRCR_DIGITAL_RESET_MASK 0x8000
#define PHY_TI_PHYRCR_DIGITAL_RESTART_MASK 0x4000

#define PHY_MODEL_TI_DP83822 0x24
#define PHY_MODEL_MASK 0x3F
#define PHY_MODEL_SHIFT 0x4

#define PHY_MODEL_TI_DP83822_LEDCR 0x18
#define PHY_MODEL_TI_DP83822_OVRLED0_EN 0x10
#define PHY_MODEL_TI_DP83822_OVRLED0_ON 0x02

#define PHY_MODEL_TI_DP83822_CR1 0x09
#define PHY_MODEL_TI_DP83822_LINKLOSSREC_EN 0x80
#define PHY_MODEL_TI_DP83822_FASTAUTOMDIX_EN 0x40
#define PHY_MODEL_TI_DP83822_ROBUSTAUTOMDIX_EN 0x20
#define PHY_MODEL_TI_DP83822_FASTAUTONEGO_EN 0x10

#define PHY_MODEL_TI_DP83822_CR2 0x0A
#define PHY_MODEL_TI_DP83822_100BASE_FX_EN 0x4000
#define PHY_MODEL_TI_DP83822_EXT_FULL_DUPLEX_ABILITY_EN 0x0020

#define PHY_MODEL_TI_DP83822_CR3 0x0B

#define PHY_MODEL_TI_DP83822_RCSR 0x17
#define PHY_MODEL_TI_DP83822_RGMII_RX_CLCK_SHIFT_EN 0x1000
#define PHY_MODEL_TI_DP83822_RGMII_TX_CLCK_SHIFT_EN 0x0800
#define PHY_MODEL_TI_DP83822_RGMII_MODE_EN 0x0200
#define PHY_MODEL_TI_DP83822_RGMII_50MHZ_CLCK_SEL 0x0080

#define PHY_MODEL_TI_DP83822_PHYCR 0x19
#define PHY_MODEL_TI_DP83822_AUTOMDIX_EN 0x8000
#define PHY_MODEL_TI_DP83822_LEDCFG_MODE1_EN 0x0020

#define PHY_RESET_MAX_WAIT_TIME 1000000000
#define PHY_RESET_MIN_WAIT_TIME 10000

#define DEBUG_ETHERNET 1

uint32_t configure_IEEE_phy_speed_US( XEmacPs * xemacpsp, unsigned speed, u32 phy_addr )
{
uint16_t phyregtemp, phyregtempcheck;
uint16_t control;
uint16_t phy_identity;
uint16_t phy_model;
uint32_t RetStatus;
volatile uint32_t wait = 0;


/* Perform a reset of the chip equivalent to HW reset */
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_TI_PHYRCR , (uint16_t *) &phyregtemp );
phyregtemp |= PHY_TI_PHYRCR_DIGITAL_RESET_MASK;
XEmacPs_PhyWrite( xemacpsp, phy_addr, PHY_TI_PHYRCR, phyregtemp );
// RetStatus = XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_TI_PHYRCR, (uint16_t *) &phyregtemp );
//
// if( RetStatus != XST_SUCCESS )
// {
// xil_printf( "Error during digital restart \n\r" );
// return XST_FAILURE;
// }
/* Wait for reset to complete */
wait = 0;
while(wait++ < PHY_RESET_MAX_WAIT_TIME)
{
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_TI_PHYRCR, (uint16_t *) &phyregtemp );
if(((phyregtemp & PHY_TI_PHYRCR_DIGITAL_RESET_MASK) == 0x00) && (wait >= PHY_RESET_MIN_WAIT_TIME))
break;
}

if( wait >= PHY_RESET_MAX_WAIT_TIME )// Reset did not complete on time
{
xil_printf( "Error during reset \n\r" );
return XST_FAILURE;
}

/* Perform PCS registers reset - probably redundant after 1st reset */
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_TI_BMCCR, (uint16_t *) &phyregtemp );
phyregtemp |= 0x8000;
XEmacPs_PhyWrite( xemacpsp, phy_addr, PHY_TI_BMCCR, phyregtemp );

/* Wait for reset to complete */
wait = 0;
while(wait++ < PHY_RESET_MAX_WAIT_TIME)
{
XEmacPs_PhyRead( xemacpsp, phy_addr, 0, (uint16_t *) &phyregtemp );
if(((phyregtemp & PHY_TI_BMCCR_RESET_MASK) == 0x00) && (wait >= PHY_RESET_MIN_WAIT_TIME))
break;
}

if( wait >= PHY_RESET_MAX_WAIT_TIME )// Reset did not complete on time
{
xil_printf( "Error during PCS registers reset \n\r" );
return XST_FAILURE;
}

// Get device identity
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_IDENTIFIER_1_REG, &phy_identity );

//Get device model
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_IDENTIFIER_2_REG, &phy_model );
phy_model = ((phy_model >> PHY_MODEL_SHIFT) & PHY_MODEL_MASK);

if(PHY_TI_IDENTIFIER == phy_identity)
{
switch(phy_model)
{
case PHY_MODEL_TI_DP83822: // MK4 BMU HW PHY

// Setup Basic mode control register to enable Auto negotiation
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_TI_BMCCR, (uint16_t *)&phyregtemp );
phyregtemp |= PHY_MODEL_TI_DP83822_AUTONEGO_EN;
XEmacPs_PhyWrite( xemacpsp, phy_addr, PHY_TI_BMCCR, phyregtemp );

#if defined(DEBUG_ETHERNET) && (DEBUG_ETHERNET == 1)
// Check init
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_TI_BMCCR, (uint16_t *)&phyregtempcheck );
xil_printf("Reg Adress in PHY %x - setup : %x - value : %x\n", PHY_TI_BMCCR, phyregtemp, phyregtempcheck);
#endif

// Setup control register 1 for link loss recovery enable etc
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_CR1, (uint16_t *)&phyregtemp );
// phyregtemp |= (PHY_MODEL_TI_DP83822_LINKLOSSREC_EN |
// PHY_MODEL_TI_DP83822_FASTAUTOMDIX_EN |
// PHY_MODEL_TI_DP83822_ROBUSTAUTOMDIX_EN);
phyregtemp |= (PHY_MODEL_TI_DP83822_FASTAUTOMDIX_EN |
PHY_MODEL_TI_DP83822_ROBUSTAUTOMDIX_EN);
phyregtemp &= ~PHY_MODEL_TI_DP83822_FASTAUTONEGO_EN;// Disable fast auto neg
XEmacPs_PhyWrite( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_CR1, phyregtemp );

#if defined(DEBUG_ETHERNET) && (DEBUG_ETHERNET == 1)
// Check init
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_CR1, (uint16_t *)&phyregtempcheck );
xil_printf("Reg Adress in PHY %x - setup : %x - value : %x\n", PHY_MODEL_TI_DP83822_CR1, phyregtemp, phyregtempcheck);
#endif

// Enable 100Mbps capability
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_CR2, (uint16_t *)&phyregtemp );
phyregtemp |= PHY_MODEL_TI_DP83822_100BASE_FX_EN;
phyregtemp |= PHY_MODEL_TI_DP83822_EXT_FULL_DUPLEX_ABILITY_EN;
XEmacPs_PhyWrite( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_CR2, phyregtemp );

#if defined(DEBUG_ETHERNET) && (DEBUG_ETHERNET == 1)
// Check init
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_CR2, (uint16_t *)&phyregtempcheck );
xil_printf("Reg Adress in PHY %x - setup : %x - value : %x\n", PHY_MODEL_TI_DP83822_CR2, phyregtemp, phyregtempcheck);
#endif
// Disable fast link down options
XEmacPs_PhyWrite( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_CR3, 0x0 );

#if defined(DEBUG_ETHERNET) && (DEBUG_ETHERNET == 1)
// Check init
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_CR3, (uint16_t *)&phyregtempcheck );
xil_printf("Reg Adress in PHY %x - setup : %x - value : %x\n", PHY_MODEL_TI_DP83822_CR3, phyregtemp, phyregtempcheck);
#endif

// Setup device in RGMII Mode
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_RCSR, (uint16_t *)&phyregtemp );
phyregtemp &=~PHY_MODEL_TI_DP83822_RGMII_RX_CLCK_SHIFT_EN; // Disable RX clock shift
phyregtemp &=~PHY_MODEL_TI_DP83822_RGMII_TX_CLCK_SHIFT_EN; // Disable TX clock shift
phyregtemp |= PHY_MODEL_TI_DP83822_RGMII_MODE_EN; // HW interface on board is RGMII
phyregtemp &= ~PHY_MODEL_TI_DP83822_RGMII_50MHZ_CLCK_SEL; // make sure clck used is 25MHz
XEmacPs_PhyWrite( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_RCSR, phyregtemp );

#if defined(DEBUG_ETHERNET) && (DEBUG_ETHERNET == 1)
// Check init
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_RCSR, (uint16_t *)&phyregtempcheck );
xil_printf("Reg Adress in PHY %x - setup : %x - value : %x\n", PHY_MODEL_TI_DP83822_RCSR, phyregtemp, phyregtempcheck);
#endif
// Setup Auto MDI enable and LED to blink in activity
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_PHYCR, (uint16_t *)&phyregtemp );
phyregtemp |= PHY_MODEL_TI_DP83822_AUTOMDIX_EN; // Enable auto MDIX in case we have crossed pairs
phyregtemp &= ~PHY_MODEL_TI_DP83822_LEDCFG_MODE1_EN; // Mode 2 : Have Led0 ON on link and blinking on Tx activity
XEmacPs_PhyWrite( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_PHYCR, phyregtemp );

#if defined(DEBUG_ETHERNET) && (DEBUG_ETHERNET == 1)
// Check init
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_MODEL_TI_DP83822_PHYCR, (uint16_t *)&phyregtempcheck );
xil_printf("Reg Adress in PHY %x - setup : %x - value : %x\n", PHY_MODEL_TI_DP83822_PHYCR, phyregtemp, phyregtempcheck);
#endif
break;

default:
xil_printf( "Network device not supported \n\r" );
return XST_FAILURE;
break;
}
}
else
{
xil_printf( "Network device not supported \n\r" );
return XST_FAILURE;
}
//
// XEmacPs_PhyWrite( xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2 );
// XEmacPs_PhyRead( xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control );
// control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK;
// XEmacPs_PhyWrite( xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control );

// XEmacPs_PhyWrite( xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0 );

XEmacPs_PhyRead( xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control );
control |= IEEE_ASYMMETRIC_PAUSE_MASK;
control |= IEEE_PAUSE_MASK;
XEmacPs_PhyWrite( xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control );

// XEmacPs_PhyRead( xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control );
// control &= ~IEEE_CTRL_LINKSPEED_1000M;
// control &= ~IEEE_CTRL_LINKSPEED_100M;
// control &= ~IEEE_CTRL_LINKSPEED_10M;

if( speed == 1000 )
{
//control |= IEEE_CTRL_LINKSPEED_1000M;
xil_printf( "1000Mbps speed not supported \n\r" );
return XST_FAILURE;
}
else if( speed == 100 )
{
//control |= IEEE_CTRL_LINKSPEED_100M;
/* Dont advertise PHY speed of 1000 Mbps */
//XEmacPs_PhyWrite( xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, 0 );
/* Dont advertise PHY speed of 10 Mbps */
XEmacPs_PhyWrite( xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, ADVERTISE_100 );
}

else if( speed == 10 )
{
//control |= IEEE_CTRL_LINKSPEED_10M;
/* Dont advertise PHY speed of 1000 Mbps */
//XEmacPs_PhyWrite( xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, 0 );
/* Dont advertise PHY speed of 100 Mbps */
XEmacPs_PhyWrite( xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, ADVERTISE_10 );
}

/* Perform a digital restart */
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_TI_PHYRCR , (uint16_t *) &phyregtemp );
phyregtemp |= PHY_TI_PHYRCR_DIGITAL_RESTART_MASK;
XEmacPs_PhyWrite( xemacpsp, phy_addr, PHY_TI_PHYRCR, phyregtemp );
// RetStatus = XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_TI_PHYRCR, (uint16_t *) &phyregtemp );
//
// if( RetStatus != XST_SUCCESS )
// {
// xil_printf( "Error during digital restart \n\r" );
// return XST_FAILURE;
// }
/* Wait for reset to complete */
wait = 0;
while(wait++ < PHY_RESET_MAX_WAIT_TIME)
{
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_TI_PHYRCR, (uint16_t *) &phyregtemp );
if(((phyregtemp & PHY_TI_PHYRCR_DIGITAL_RESTART_MASK) == 0x00) && (wait >= PHY_RESET_MIN_WAIT_TIME))
break;
}

if( wait >= PHY_RESET_MAX_WAIT_TIME )// Reset did not complete on time
{
xil_printf( "Error during digital restart \n\r" );
return XST_FAILURE;
}

//XEmacPs_PhyWrite( xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control | IEEE_CTRL_RESET_MASK );
// Query to restart autonego
XEmacPs_PhyRead( xemacpsp, phy_addr, PHY_TI_BMCCR, (uint16_t *)&phyregtemp );
phyregtemp |= PHY_MODEL_TI_DP83822_AUTONEGO_RESTART;
XEmacPs_PhyWrite( xemacpsp, phy_addr, PHY_TI_BMCCR, phyregtemp );

// for( wait = 0; wait < 100000; wait++ );
xil_printf( "\nPHY init sequence done ! \n\r" );
return XST_SUCCESS;
}

Here is a dump of the registers :

Reg 0x0 act value : 0x1100

Reg 0x1 act value : 0x7849

Reg 0x2 act value : 0x2000
Reg 0x3 act value : 0xA240
Reg 0x4 act value : 0x0180
Reg 0x5 act value : 0x0000
Reg 0x6 act value : 0x0004
Reg 0x7 act value : 0x2001
Reg 0x8 act value : 0x0000
Reg 0x9 act value : 0x0060
Reg 0xA act value : 0x4120
Reg 0xB act value : 0x0000
Reg 0xC act value : 0x0000
Reg 0xD act value : 0x401F
Reg 0xE act value : 0x0005
Reg 0xF act value : 0x0000
Reg 0x10 act value : 0x0206
Reg 0x11 act value : 0x0108
Reg 0x12 act value : 0x0000
Reg 0x13 act value : 0x0000
Reg 0x14 act value : 0x0000
Reg 0x15 act value : 0x0000
Reg 0x16 act value : 0x0100
Reg 0x17 act value : 0x0241
Reg 0x18 act value : 0x0400
Reg 0x19 act value : 0x8001
Reg 0x1A act value : 0x0000
Reg 0x1B act value : 0x007D
Reg 0x1C act value : 0x05EE
Reg 0x1D act value : 0x0000
Reg 0x1E act value : 0x0002
Reg 0x1F act value : 0x0000
Reg 0x461 act value : 0x0410
Reg 0x462 act value : 0x0000
Reg 0x467 act value : 0x5FD3
Reg 0x468 act value : 0x0005

I can't see anything wrong my side and can't figure out why at least the PC would not recognize the connection.

For info powering up a ZCU 104 eval board using a DP83867 in JTAG mode without any code running, at least the PC detects the connection on a unidentified network.

Would someone be able to point me in the right direction ?

Thanks

Seb

  • 0
    TI__Expert 7040 points

    Hi Sebastien,

    Can you confirm the following settings? 

    • Auto-negotiation is disabled through bootstrap settings.
    • Register 0x467 indicates RX_DV is strapped into mode 2 (0x0467[5:4]=01). This is a reserved state in Table 14 of the DP83822 datasheet. Can you confirm the desired MAC interface?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Intellectual 290 points

    Hi Justin

    Thanks for your  feedback.

    There is no boot strap on the board. HW team intended a full SW config. I can send extract of schematic if required.

    All signals of the interface are pulled up by default in the FPGA.

    Desired interface is RGMII with MAC.

    I'm trying to enable RGMII using register 0x0017 bit 9.

    Regards

    Seb

  • 0 in reply to Sebastien Chapeau
    TI__Expert 7040 points

    Hi Seb,

    What register are you referring to to indicate the PHY is not showing a cable is connected? 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Intellectual 290 points

    Hi Justin

    I  can get to a point where Link Status shows OK in BMSR.

    Auto negotiation process complete BMSR bit 5 never comes to 1.

    When I say disconnected it corresponds to the PC status showing "cable unplugged".

    In parallel of our custom board, I have made some tests with a ZCU106 using a DP83867.

    The HW uses boot straps but I played with initialization of the chip and I can see the PC status reacting to  the changes made to the chip when stepping through the initialization.

    I can't see the same with the DP83822 on our custom board.

    Why would link status show OK but PC not see cable is unplugged ? Did I do something wrong in the init sequence of the chip ?

    Thanks in advance for your help.

    Regards

    Seb

  • 0 in reply to Sebastien Chapeau
    TI__Expert 7040 points

    Hi Seb,

    Can you provide a register comparison between a setup with link okay and one with no link? When initializing the PHY, can you check that the power rails are ramped from GND to VDD without a plateau and that a digital reset is done after configuring the registers to set the PHY into the proper mode? 

    I agree that it is odd the PHY would show link okay and PC show no connection. Can you please also provide the schematic to review? 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Intellectual 290 points

    Hi

    The register setup does not change between a situation where I get Link OK and a situation where link OK never go to true.

    What changes is the init sequence. In one case where I get link OK I do a Digital restart 

    Case 1 as shown in 1st thread is :

    - PHY reset Reg 0x001F |= 0x8000

    - PCS reg reset Reg 0x001 |= 0x8000

    - Register setup 

    - Digital restart Reg 0x001F |= 0x4000

    Case 2 is :

    - PHY reset and PCS reg reset replaced by Digital restart Reg 0x001F |= 0x4000

    - Register setup as per code shown in 1st thread

    - Digital restart Reg 0x001F |= 0x4000

    What ever case I'm in PC will shown cable is disconnected even if crossed pair detection is activated. We checked the wiring from board to PC it is ok.

    For the schematic, can you provide a private link for me to share this ? Should we disable the pull ups in FPGA or set them to pull down ?

    I will take the measurements and come back to you.

    Regards

    Seb

  • 0 in reply to Sebastien Chapeau
    TI__Expert 7040 points

    Hi Seb, 

    I'm sorry for the confusion, can you provide the register status of the PHY when link is shown? This will help me understand the auto-negotiation, MDI/X, and link partner capabilities.

    I would recommend putting all FPGA pins interfacing the PHY in a Hi-Z mode to not override the internal straps of the PHY. This may be putting the PHY into a intermediate strap mode or resereved state. Please also confirm if the LED pins are being used and if there is a pull-up or pull-down resistor associated with them? 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Intellectual 290 points

    Hi Justin

    Thanks for your advices.

    We will do a tets were pull up are put in HiZ and let you know the outcome. I will also send the reg dump with the init sequence that allows link to be ok.

    For the LED, only Led0 is used. No pull up of pull down. Just the LED with a 2.2K polarization resistor.

    Led1 / GPIO1 , COL/GPIO2, INT/PWDN_N , RX_ER, CRS/CRS_DV are left unconnected.

    Regards

    Seb

  • 0 in reply to Sebastien Chapeau
    Intellectual 290 points

    Hi Justin

    We put the FPGA pins in high Z disabling any pull up or pull down on the device interfaces.

    The initialisation for the device gives the following:

    Reg Adress in PHY 0 - setup : 3100 - value : 3100
    Reg Adress in PHY 9 - setup : 60 - value : 60
    Reg Adress in PHY A - setup : 4120 - value : 4120
    Reg Adress in PHY B - setup : 1000 - value : 1000
    Reg Adress in PHY 17 - setup : 241 - value : 241
    Reg Adress in PHY 19 - setup : A001 - value : A001
    Waiting for PHY to complete autonegotiation.-----> Time allocated is 30sec.
    Auto negotiation error
    link speed: 100

    First register dump after init - PC is still showing the cable is unplugged:

    Reg 0x0 act value : 0x3100
    Reg 0x1 act value : 0x7849
    Reg 0x2 act value : 0x2000
    Reg 0x3 act value : 0xA240
    Reg 0x4 act value : 0x0DE1
    Reg 0x5 act value : 0x0000
    Reg 0x6 act value : 0x0004
    Reg 0x7 act value : 0x2001
    Reg 0x8 act value : 0x0000
    Reg 0x9 act value : 0x0060
    Reg 0xA act value : 0x4120
    Reg 0xB act value : 0x1000
    Reg 0xC act value : 0x0000
    Reg 0xD act value : 0x0000
    Reg 0xE act value : 0x0000
    Reg 0xF act value : 0x0000
    Reg 0x10 act value : 0x2804
    Reg 0x11 act value : 0x0108
    Reg 0x12 act value : 0xA300
    Reg 0x13 act value : 0x0800
    Reg 0x14 act value : 0x0000
    Reg 0x15 act value : 0xFFFF
    Reg 0x16 act value : 0x0100
    Reg 0x17 act value : 0x0241
    Reg 0x18 act value : 0x0400
    Reg 0x19 act value : 0xA001
    Reg 0x1A act value : 0x0000
    Reg 0x1B act value : 0x007D
    Reg 0x1C act value : 0x05EE
    Reg 0x1D act value : 0x0000
    Reg 0x1E act value : 0x0002
    Reg 0x1F act value : 0x0000
    Reg 0x461 act value : 0x0410
    Reg 0x462 act value : 0x0000
    Reg 0x467 act value : 0x0FD3

    Register dump after unplugging and plugging the cable again - Link becomes OK - TCP-IP stack initializes OK.

    PC is still showing the cable is unplugged(!?):

    UDPInterface_InitialiseSockets
    UDPInterface_Open
    UDPInterface_Open: Bind to 192.168.10.78 Port 8000h
    UDPInterface_Open: OK

    Reg 0x0 act value : 0x3100
    Reg 0x1 act value : 0x784D
    Reg 0x2 act value : 0x2000
    Reg 0x3 act value : 0xA240
    Reg 0x4 act value : 0x0DE1
    Reg 0x5 act value : 0x0000
    Reg 0x6 act value : 0x0004
    Reg 0x7 act value : 0x2001
    Reg 0x8 act value : 0x0000
    Reg 0x9 act value : 0x0060
    Reg 0xA act value : 0x4120
    Reg 0xB act value : 0x1000
    Reg 0xC act value : 0x0000
    Reg 0xD act value : 0x401F
    Reg 0xE act value : 0x0000
    Reg 0xF act value : 0x0000
    Reg 0x10 act value : 0x2A05
    Reg 0x11 act value : 0x0108
    Reg 0x12 act value : 0x8300
    Reg 0x13 act value : 0x0000
    Reg 0x14 act value : 0x00FF
    Reg 0x15 act value : 0xFFFF
    Reg 0x16 act value : 0x0100
    Reg 0x17 act value : 0x0249
    Reg 0x18 act value : 0x0400
    Reg 0x19 act value : 0xA001
    Reg 0x1A act value : 0x0000
    Reg 0x1B act value : 0x007D
    Reg 0x1C act value : 0x05EE
    Reg 0x1D act value : 0x0000
    Reg 0x1E act value : 0x0002
    Reg 0x1F act value : 0x0000
    Reg 0x461 act value : 0x0410
    Reg 0x462 act value : 0x0000
    Reg 0x467 act value : 0x0FD3
    Reg 0x468 act value : 0x0000

    I'm completely puzzled by this behavior. Looking at reg 0x467, it is looking the devices latches on RMII interface with 50MHz clock source.

    From the setup register 0x17, RGMII interface is enabled and clock is selected at 25MHz which is the correct setup for the HW.

    Can't understand what's wrong.

    I hope you would have any pointer to help us.

    Regards

    Seb

  • 0 in reply to Sebastien Chapeau
    TI__Expert 7040 points

    Hi Seb,

    I will need time to review the register information. I can provide a response by Friday 1/29.

    Regards,
    Justin

  • 0 in reply to Justin Lazaruk
    Intellectual 290 points

    Hi 

    Thanks for that. 

    A question form us What could cause the chip would see link OK but PC see the cable is unplugged ?

    Thanks

    Seb

  • 0 in reply to Justin Lazaruk
    Intellectual 290 points

    Hi Justin

    Breakthrough here. We finally got the PHY to work properly.

    So a few things made the trick:

    - FPGA was build with pull up / pull down disabled.

    - 1st step of the init sequence is a HW reset (reg 0x1F / bit 15 set to one) with a loop to wait for the reset to complete.

    this is to make sure we clean off any state the PHY would latch up on after power up.

    - Fiber mode was enabled by mistake (Reg 0x00A / bit 14). I made sure to disable this one. With that bit disabled the PC could actually the cable was connected.

    - Disable the clock shift on the TX path to be able to transmit packets (Reg 0x17 / bit 11 set to 0)

    - Enable the clock shift on the RX path for the mac to be able to receive packets (Reg 0x17 / bit 12 set to 1)

    And now it works.

    Thanks a lot for all your help.

    Regards

    Seb