Customer confused that “For splitter mode with external REFCLK, the most basic option is to use REFCLK0 = PCLK0 and REFCLK1=PCLK1.”in 941AS datasheet, however，datasheet also describes that "only in independent 2：2 mode，you can configure REFCLK0 = PCLK0 and REFCLK1=PCLK1“，then in single DSI split screen condition， how to configure REFCLK0 = PCLK0 and REFCLK1=PCLK1？target purpose is that it can configure REFCLK0 & REFCLK1 up to105M, to support per port .
BTW，customer thinks that, clock mode is 01, the mean is External Reference Clock Mode, then according to 0x3e,0x3f description，put external clock in fractional frequency at least 2 fractional frequency，the mean is REFCLK0 = REFCLK1 = 210M, then according to fractional frequency, per port pclk up to 105M， in this condition， external input clock should be configured to a maximum of 210M. Is it right ?
