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DS90UH941AS-Q1: Internal pattern generation with internal clk and external clk

Roy Chou1
Genius 16110 points
Part Number: DS90UH941AS-Q1

Hi Team,

I would like to check below connection. 941+948(dual lane)

1. internal pattern generation with external clk, where should I connect the external clk? DSI0_CLK or DSI1_CLK?

2. REFCLK0/1 short to GND if I dont use splitter mode, is it correct?

3. internal pattern generation with internal clk, Could DSI0/1_CLK leave floating? or they should connect to GND only?

4. If I use VDDIO=3.3V to let I2C operate in 3.3Vmode. Does it mean that GPIO's VIH, VIL is followed by 3.3V condition? Any other connection should be concerned?

Roy

  • 0
    TI__Guru** 108100 points

    Hello Roy,

    1) This depends on which input port you are using. If a single input then it should be on DSI0_CLK in this case.

    2) you can leave them as NC or short to GND.

    3) leave them floating.

    4) I2C voltage is independent from VDDIO. You can use either 1V8 or 3V3 on either of pins.

  • 0 in reply to Hamzeh Jaradat
    TI__Genius 16110 points

    Hi Jaradat,

    For question#1, what does "input port" mean? We will only use internal pattern generation which means there is not DSI data input to 941AS-Q1 and we will use dual lane via FPD-link. For PCLK, we will use external clk. So which pin should we connect the external clk. And we dont need to use REF, is it correct?

    1. Only DSI0_CLKP/N?

    2. Only DSI1_CLKP/N?

    3. Both of DSI0_CLKP/N and DSI1_CLKP/N?

    Roy

  • 0 in reply to Roy Chou1
    TI__Guru** 108100 points

    Hello Roy,

    You said, you want to use Internal Pattern with EXTERNAL CLK. That means you are using the INPUT PORT to feed this CLK. Correct?

    So, as I said;  This depends on which input port you are using. If a single input then you should use the DSI0_CLK  only.

  • 0 in reply to Hamzeh Jaradat
    TI__Genius 16110 points

    Hi Jaradat,

    Excuse me. I don't understand your meaning. If we use internal pattern generation which means the pattern is generated by 941AS-Q1. 

    What is the relation between DSI input port and internal pattern generation? 

    Regards,

    Roy

  • 0 in reply to Roy Chou1
    TI__Guru** 108100 points

    Hello Roy,

    You can use the internal pattern generator, but still you need to chose if you want to use the EXTERNAL CLK or the Internal CLK.

    Same thing, you need to chose if using External or Internal timing (HSynch/VSynch) for you generated pattern.

    Please refer to the AppNote, page 3 (section 2).

  • 0 in reply to Hamzeh Jaradat
    TI__Genius 16110 points

    Hi Hamzeh,

    I understand you meaning. But I still have question about external clk setting. I re-clarify my question again.

    In 947, we use internal pattern gen with external clk. We connect external clk on pin57/58 clk+/-.

    But in 941, we find there is two clk input, DSI0CLK and DSI1CLK.

    So my question is which pin should be connected to CLK, DSI0CLK or DSI1CLK.

    And internal pattern gen doesnt need DSI data input, why you reply "If a single input then it should be on DSI0_CLK in this case"

    But we don't have data input, isn't it?

    Regards.

    Roy

  • 0 in reply to Roy Chou1
    TI__Guru** 108100 points

    Hello Roy,

    please use DSI0CLK for your PCLK input.