DS90UH941AS-Q1: Internal pattern generation with internal clk and external clk

Hi Jaradat,

For question#1, what does "input port" mean? We will only use internal pattern generation which means there is not DSI data input to 941AS-Q1 and we will use dual lane via FPD-link. For PCLK, we will use external clk. So which pin should we connect the external clk. And we dont need to use REF, is it correct?

1. Only DSI0_CLKP/N?

2. Only DSI1_CLKP/N?

3. Both of DSI0_CLKP/N and DSI1_CLKP/N?

Roy

Hi Jaradat,

Excuse me. I don't understand your meaning. If we use internal pattern generation which means the pattern is generated by 941AS-Q1. 

What is the relation between DSI input port and internal pattern generation? 

Regards,

Roy

Hello Roy,

You can use the internal pattern generator, but still you need to chose if you want to use the EXTERNAL CLK or the Internal CLK.

Same thing, you need to chose if using External or Internal timing (HSynch/VSynch) for you generated pattern.

Please refer to the AppNote, page 3 (section 2).

Hi Hamzeh,

I understand you meaning. But I still have question about external clk setting. I re-clarify my question again.

In 947, we use internal pattern gen with external clk. We connect external clk on pin57/58 clk+/-.

But in 941, we find there is two clk input, DSI0CLK and DSI1CLK.

So my question is which pin should be connected to CLK, DSI0CLK or DSI1CLK.

And internal pattern gen doesnt need DSI data input, why you reply "If a single input then it should be on DSI0_CLK in this case"

But we don't have data input, isn't it?

Regards.

Roy

Hello Roy,

please use DSI0CLK for your PCLK input.