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DP83867E: immunity to a clock frequency offset of a link partner

Cyril Strejc
Prodigy 50 points
Part Number: DP83867E

Dear TI support,

Observation: DP83867E is not able to establish Ethernet link in 100BASE-TX mode if an IEEE non-compliant link partner has +280 PPM stable frequency offset (typically 25.007089 MHz).

Question: Is it possible to tweak DP83867E, possibly by software means via register access, to be able to establish reliable 100BASE-TX Ethernet link to the IEEE non-complaint link partner with the inaccurate oscillator having the constant frequency offset (+280 ppm)?

Reproducibility: It is possible to use an evaluation board DP83867ERGZ-S-EVM and the non-compliant device to reproduce the observation. On the other hand, PHYs by other vendors we have tested can accept the +280 PPM link partner clock frequency offset.

Rationale: We need to integrate our devices with DP83867Es into an existing customer infrastructure. In the existing infrastructure there is a bunch of non-compliant devices with the inaccurate oscillator mentioned above. We cannot repair the customer's devices and we are supposed to solve the issue on our side with DP83867E.

 

Thank You,

Cyril

  • 0
    TI__Expert 7040 points

    Hi Cyril,

    The we cannot confirm the functionality of the DP83867 with a non-standard link partner with a ppm +280, this is outside the datasheet specification and our own validation testing. However, as a test, you can set the DP83867 reference clock to 25MHz +100ppm to narrow the difference between the PHY and the link partner. 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 50 points

    Hi Justin,

    as the test you suggested, we set DP83867E reference clock to 25MHz + 100ppm. With this reference clock frequency, DP83867E is able to establish Ethernet link with the non-compliant 25MHz + 280ppm link partner.

    Observation: Minimum DP83867E reference clock frequency needed to establish Ethernet link with the link partner is 25MHz + 40ppm, which means DP83867E is able to consume 240ppm difference in link partners reference clock frequencies (where IEEE defines 200ppm as the maximum allowed frequency difference, so there is 40ppm margin for an error).

    Question: Is it be possible to configure DP83867E via register access to be more tolerant to link partners frequency difference?

    Thank You,

    Cyril

  • 0 in reply to Cyril Strejc
    TI__Expert 7040 points

    Hi Cyril,

    I'm glad to hear the setup is working now. We do not have characterization data increasing the frequency tolerance of the device outside of the IEEE specification or DP83867 datasheet.

    Regards,
    Justin