Hi
1. Whether the shutdown of logic electrical VDD will affect the INT interrupt
2. Can VDD be turned off at low power consumption
3. When configured to Polling mode, input interrupt is opened, INT will always be low, what is the reason for this phenomenon?
4. Can you provide routine
thanks！
Hi Neal,
I have
1. Whether the shutdown of logic electrical VDD will affect the INT interrupt
The INT pin is an open drain architecture and will require an external pull up resistor to use for the logic high. The VDD logic supply is used to set the logic level of the SPI signals connected to the MCU and can be used for the INT pullup resistor as well. However, the INT pin could be connected to the 12V supply as well if it needs to be active when VDD is disabled. Section 8.3.9.3 of the datasheet called Microcontroller Wake-Up describes how this is accomplished and Figure 15 of the TIC10024-Q1 datasheet shows the circuit.
If there is only a pullup resistor to VDD and the VDD supply is shutdown, then there will be no indication of the INT signal to the MCU.
2. Can VDD be turned off at low power consumption
Yes, the VDD only sets the logic levels for the SPI and INT if it is used for the pullup supply. The device is fully powered from the Vs Supply and will retain the configuration settings. However, VDD must be present in order for proper SPI communication, but it can be turned off when SPI communication is not needed. INT will need the VDD supply unless it has been configured with a pullup to the Vs supply as outlined in the datasheet.
3. When configured to Polling mode, input interrupt is opened, INT will always be low, what is the reason for this phenomenon?
I am not sure if I am correct in my understanding of your question, but I think you are referring to the following behavior.
After the TRIGGER bit is set to 1, the device will poll the input and store the default switch state values into memory. When this is complete it will set the SSC bit in the INT_STAT register and set the INT pin low to indicate that the device is now actively monitoring the input switches for changes from their default states. To clear the INT pin the MCU must read the INT_STAT register (Offset = 2h) to clear the SSC bit which will in turn release the INT pin from the low state.
If this is not what you are referring to, please either point to the documentation, or provide some additional information about the configuration and your attempts to release the INT pin that are unsuccessful to help me understand.
4. Can you provide routine
I can help provide a routine or some configuration suggestions. But I’m not sure what you are specifically asking for. Did you just want information on how to release the INT pin? If so you simply need to read the INT_STAT register.
Regards,
Jonathan
Hi Neal,
Q1 is a PNP BJT transistor and the figure in the datasheet is correct, but your suggestion will work as well.
Here is a simulation of the circuit shown in the datasheet with the Emitter connected to the LDO_EN using a square wave signal to represent the nINT pin's output.
And here is a simulation of your suggested configuration with the collector connected to the LDO_EN.
You can see that both configurations should work and I did a quick prototype of this circuit using a breadboard to verify that both configurations do in fact work as shown in the simulations.
Please read the Steps to Configure TIC12400-Q1 Multiple Switch Detection Interface (MSDI) Application Report for information on how to configure the device. I do not have any information on your desired configuration with regards to the inputs you are going to use, whether you are going to source or sink current, and how much current you will need, whether you are going to use the comparator or ADC for the sampling and what thresholds you will need for the types of switches, etc.
The application report will walk you through the configuration steps, but if you have any additional questions regarding any of the details, please let me know.
Regards,
Jonathan
