PROCESSOR-SDK-DRA8X-TDA4X: How to make 1000M Ethernet CPSW works

Hi,

Can you provide more details ? I am assuming it's a custom board (correct me if wrong)

1. Which SDK version are you running ?

2. Are you running Linux or RTOS ? Which Core ?

3. Which CPSW is it ? CPSW 9G or MCU CPSW ?

4. Both of the CPSW's support Gigabit out of the box. Assuming that you have the PHY mode configured correctly and have 100M working, it should work out of the box.

5. Do you have access to an EVM ? You can check out the demo which is part of SDK.

Regards

Vineet

Hi Vineet,

Thanks for your reply.

I am assuming it's a custom board (correct me if wrong)

yes, it is the customed board.

1. Which SDK version are you running ?

psdk7.01.

2. Are you running Linux or RTOS ? Which Core ?

the ethernet driver is running on RTOS, R5f0_0 core.

3. Which CPSW is it ? CPSW 9G or MCU CPSW ?

it is CPSW 9G.

4. Both of the CPSW's support Gigabit out of the box. Assuming that you have the PHY mode configured correctly and have 100M working, it should work out of the box.

We have tried to make a pcs loopback on phy, which make the mac part isolated with the phy. The phy status detected by cpsw9g is 1G linked up, also we applied the mac loopback by configuring the mac ctrl register; the result is that the txclk is 125Mhz, but we can not seen any packets received by cpsw9g.