SN65DSI86: display screen abnormal phenomena,

Hi,

I can't tell from the screen capture, what value are you writing to 0x0A, 0x5C, 0x77, and 0x78? And what values are you reading back from these registers? Are the read back value consistent each time?

Thanks

David

Hi

sorry，My question is that there is an abnormality on the display screen,what may be the cause?

The register values to be written are below，The wrong value to read ，is  5C 77 78，

The register reads the wrong value. What causes it? Is it related to the abnormal   display screen?

thanks！

Hi, 

What particular abnormal issue do you have with the DSI86?

If you have the panel EDID information, please use the spreadsheet to generate the DSI86 registers programming values. You can download the spreadsheet at:

I would recommend enabling the DSI86 color bar. The color bar is internally generated by the DSI86 and helps to separate the issue between the DSI and eDP interface.

Register 0x0A bit 7 is the PLL lock indicator and would set to a '1' if the PLL is locked. But register 0x5C, 0x77, 0x78 should not change on its own.

Can I also take a look at your schematic?

Thanks

David

HI

If the color bar mode is OK and there is a problem with the display, it means there is a problem with the timing

Now the display screen will not display if it is in color bar mode,thanks!

SCH is below.

Hi,

Does the panel support ASSR? If not, you need to disable the ASSR in DSI86.

To disable ASSR, it is recommended to pull TEST2 pin to 1.8V thru a 1k to 10k resistor. Once TEST2 is high, the following steps must be performed:

1. Write 0x07 to register 0xFF. This will select Page 7.
2. Write 0x01 to register 0x16. This will make ASSR_CONTROL to be read/write.
3. Write 0x00 to register 0xFF. This will select Page 0.
4. Write 0 to bits 1:0 at register 0x5A. This will change from ASSR to Standard DP.

Thanks

David

Hi

SN65DSI86 is configured to use the CLK of channel A,

When the display screen is normally displayed, the measured CLK is about 460m, and when abnormal occurs, the measured frequency is about 920m.

What could possibly cause it?

Thanks!

Hi,

Can you please measure the clock frequency between the normal and abnormal case? The clock is generated by the MIPI source, are you seeing the clock frequency actually changes?

Thanks

David

Hi David

 Clock ,normally is 460m, abnormal  is about 920m,thanks!