Dear team,
I would like to inquire about Lan transformer and PHY Chip.
I know that the design of the Center Tap pin in LAN TRANSFORMER is pull up and pull down according to the structure of PHY's line drive is current mode logic or voltage mode logic, respectively.
If so, is there a way to know the LINE DRIVER architecture in PHY Chip? Even if I check the datasheet, the contents of LINE DRIVER architecture do not seem to come out.
In addition, in the case of pull down to LAN TRANS Center Tap PIN, nF unit of Cap is added, is it to protect errors due to excessive immunity problem, noise and specific data pattern?
I checked out the DP83848 series.
I would be very grateful for your answer.