This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83848-EP: Center tap composition according to the line driver of the phy chip

Part Number: DP83848-EP

Dear team,
I would like to inquire about Lan transformer and PHY Chip.

I know that the design of the Center Tap pin in LAN TRANSFORMER is pull up and pull down according to the structure of PHY's line drive is current mode logic or voltage mode logic, respectively.

If so, is there a way to know the LINE DRIVER architecture in PHY Chip? Even if I check the datasheet, the contents of LINE DRIVER architecture do not seem to come out.

In addition, in the case of pull down to LAN TRANS Center Tap PIN, nF unit of Cap is added, is it to protect errors due to excessive immunity problem, noise and specific data pattern?

I checked out the DP83848 series.

I would be very grateful for your answer.

  • Hello,

    The current mode line driver's tend to have external circuitry on the MDI, such as pulling the center taps up to VCC or terminations on the MDI lines. Such external circuitry is not needed for the voltage mode line driver design. The DP83848 and DP83822 are examples of TI PHYs using current mode line drivers, observe the external circuitry needed in Figure 6-2 of the DP83848-EP datasheet. 

    Yes this decoupling of the center taps is to help with EMC/EMI performance.  

    I understand you are looking into the DP83848 series. Do you have any specific PHY needs? If you are looking for an industrial 10/100 PHY, might I recommend our newe generation PHYS: DP83822, DP83825, and DP83826?

    Thank you

    Nikhil