NS16C2552: Trigger condition for incrementing Tx FIFO pointer

Hi Kato,

"So, could you please tell me the trigger condition and internal operation for incrementing Tx FIFO pointer in detail?"

Unfortunately we don't have the design database for this device anymore so we don't have a way to look at the internal timing for the device.

"I think that /WR rising edge is involved as a trigger condition."

Thats correct, the /WR is used to toggle the data into the parallel ports.

Typically you would: (Note, steps 1-4 can happen in any order)

1) set address

2) toggle /CS to LOW

3) toggle /CHSL to desired channel

4) Set parallel data you want to write

5) Toggle /WR low

6) Toggle /WR HIGH

At this point, after about 4ns, the device should have sampled the dataline and shifted the parallel bits into a shift register to serialize the data.

From here, the device should shift the parallel data through into the FIFO though I don't know if its synchronous or asynchronous with the oscillator. I would assume its synchronous though. 

-Bobby