• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 516 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB941AS-Q1: DSI data lane with 480*240 display monitor questions

Kailyn Chen
Genius 9560 points
Part Number: DS90UB941AS-Q1

Hello，

Our customer's application is as below:

SOC <--DSI--> ds90ub941 serializer <--FPDLINK--> ds90ub948 deserializer <--oLDI--> ds90cf366 <--RGB--> display monitor (480x240)
    

ds90ub941 configured CLOCK Mode 0： “FPD-Link III is generated from DSI clock. The DSI clock has to be continuous.”。

First he configured the  4 DSI data lane(by MODE_SEL0 configuration), but the display monitor couldn't appear。

And then he configured the register 0X4F and changed to 1 lane, the display could appear.

So the question is that:

1. The datasheet described the pixel clock frequency range is 25Mhz to 105 MHz over one lane. But why the 480*240 LCD could dispaly?

2.Why the data lane is changed from 4 to 1, and the LCD could display? 

 

Best regards

Kailyn

 

 

  • 0
    TI__Mastermind 19720 points

    Hi Kailyn,

    What is the total video resolution include blanking?

    Was the TSKIP value properly placed for the 4 lane?

    Regards,

    Michael W.

  • 0 in reply to Michael.Walker
    TI__Genius 9560 points

    Hi Michael,

    Thank  you for your reply. Below is the part of the LCD datasheet, and we could calculate the total pixel clock:

       (480+296)*(240+10)*60=11640000=11.64.MHz

    If it could work normally under this resolution, does it have any potential question during long work? 

    Very appreciated

    Best regards

    Kailyn

  • 0 in reply to Kailyn Chen
    TI__Mastermind 19720 points

    Hi Kailyn,

    What is the Horizontal Cycle? 

    The 25 MHz to 105 MHz PCLK is the rates between which we validate  the 941AS to work with. I do not know why your application works with the 941AS and 948 but we cannot guarantee that this system will work in all temps and all cases, so I advise not using the 941AS for this display unless you can increase the PCLK. 

    The DSI has a requirement of at least 150Mbps per lane, with 4 lanes your data per lane was below 150 Mbps per lane and with 1 lane you are over this 150 Mbps per lane requirement.

    Regards,

    Michael W.

  • 0 in reply to Michael.Walker
    TI__Genius 9560 points

    Hello Michael，

    The horizontal cycle is 504~1540 PCLK. Customer used 941 because its input is compatible with MIPI DSI input.  And we have two serializers UB941and UH941 which minimum pixel clock are both 25Mhz .

    Best regards

    Kailyn

  • 0 in reply to Kailyn Chen
    TI__Mastermind 19720 points

    Yes, but what is horizontal cycle? If the H active is 480 and the H blanking is 296 max and the max framerate is 70 Hz then the number of H pixels per sec is 54320. I dont see what horizontal cycle is.