Hi team,
Good day.
Do we have any design guidelines in connecting the DP83620SQ/NOPB to Intel Max10 FPGA through RGMII/MII interface?
Regards,
Carlo
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Carlo,
You may follow the design guidelines highlighted in the app note AN-1469. There is a section dedicated to the MAC interface design . However, there is on error in this document. Length matching should be within 50 mils maximum, not 2.0 inches.
Please let me know if you require any additional information.
Thank you,
Nikhil