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TFP401: Not seeing transmitted screen resolution

Philip Hale
Prodigy 90 points
Part Number: TFP401
Other Parts Discussed in Thread: TFP410, SN74LVC244A

I am testing a board fitted with a TFP401 chip. I am transmitting a series of test patterns to the board using DVI at 1280 x 1024 @ 60hZ from a QuantumData 780C video generator. The parallel output data from the TFP401 is taken from the test board via a parallel cable to a second circuit board where the data is buffered by SN74LVC244A octal buffers then converted back to a DVI signal by a TFP410 chip.

The issue I am seeing is that when the output of the TFP410 chip is connected to a monitor, the screen is mostly black and flickers occasionally. The set-up does function, I can see the transmitted data patterns on the monitor with output settings of up to a screen resolutions of 1280 x 720 @ 60hZ, but anything above this does not display. The ODCK is running at 108.9MhZ when 

A couple of questions:

  • With the ST pin of the TFP401 pulled high, setting the drive outputs to high strength, what is the maximum length of track that the 1280 x 1024 @ 60hZ could be expected to be driven down and still arrive as a valid signal? I am currently using a longer parallel cable than planned, and will be moving to a shorter length when it becomes available but at the moment, the length of parallel tracking between the output of the TPF401 and the SN74LVC244A octal buffers is about 30cm. Between the output of the octal buffers and the input of the TFP410 is about 1cm.
  • The webpage for the SN74LVC244A octal buffers rates them as capable of 200Mbps. Is this per data line, or spread across all eight data lines? (i.e, each data line can transmit at 25Mbps and all eight lines make up the 200Mbps).

If the above questions are not the cause of the issue, what would be other areas to investigate?

Cheers

Phil

  • 0
    TI__Mastermind 35130 points

    Hi Philip,

    It's generally recommended to keep trace lengths less than 5cm. You should also ensure to minimize any parasitic capacitance on the output traces.

    The 200 Mbps is for each channel of the buffer.

    Have you investigated the input signals of the TFP410 with an oscilloscope? 

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 90 points

    Hi,

    I have managed to fit a shorter parallel cable, this has now reduced my track lengths from about 30cm to about 15cm, and I have seen some improvement in what I'm seeing. Images are still clean only up to a resolution of 1240 x 768 @ 60hZ, but I am now seeing the pattern I am transmitting at 1280 x 1024 @ 60hZ. Unfortunately, it is the wrong colours, slightly distorted and is only present about 60% of the test time.

    I've had a look at the Hsync, Vsync, ODCK, DE and a couple of the QE signals being fed into the TFP410. Upto a resolution of 1280 x 768 @ 60hZ, the signals look clean at this point and what I'd expect them to look like. 

    Switching the resolution being handled up to 1280 x 800 @ 60hZ, the signals monitored start to become less clean, and the DE signal in particular appears to double pulse with the second pulse almost immediately after the first and the Hsync appears to have bursts of pulses occasionally occuring at much higher frequency than the rest of the signal. At a resolution of 1280 x 1024 @ 60hZ, all signals become a mess of pulses.

    Cheers

    Phil

  • 0 in reply to Philip Hale
    TI__Mastermind 35130 points

    Hi Phil,

    It looks like this is caused by the long run length. Are you able to reduce the lengths further?

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 90 points

    Hi,

    I am somewhat limited with options to reduce the run length unfortunately. The TFP401 chip is fitted to a customer card which I need to interface to. There is about 2cm of track on this card between the TFP401 and the interface connector. The shortest cable possible between the customer board and my interface board is about 6cm, with a further 4-6cm (to allow for run length matching) on the interface board.

    I have been able to improve things somewhat by adjusting the skew settings of the TFP410 chip that is receiving the data to the minimum skew settings, which has reduced the amount of blank screens that I have been seeing, but the image displayed are still corrupt.

    Part of the testing I have been performing involves a video analyser which I have just managed to get to respond to the received data. One thing that is reporting, even on low resolution (640 x 480 @ 60hZ) images that display correctly with no visible corruption is that the Hsync delay parameter is 4 greater than the analyser expects and the Hsync polarity is the opposite of the expected.

    At 640 x 480 @ hZ,  analyser expects a Hsync delay of 16, I am seeing 20. The analyser expects a negative Hsync polarity, I am seeing positive.

    Similarly for a test signal of 800 x 600 @ 60hZ, I am seeing a delay of 44, while the analyser is expecting a delay of 40 and the Hsync polarity is negative, with a positive polarity expected.

    The difference of 4 between measured and expected Hsync delay is consistent no matter what I resolution I set. Is this likely to be due to the run length too?

    Cheers

    Phil

  • 0 in reply to Philip Hale
    TI__Mastermind 35130 points

    Hi Phil,

    Run length will not change HSYNC polarity, That is something the DVI source decides and the TFP401 will just pass through as it has no control over it. The extra delay may be due to the run length though. 

    Do the signals (Hsync, Vsync, ODCK, DE) at higher resolutions still look distorted if you disconnect the 2nd circuit board with the TFP410 and SN74LVC244A and just measure the output pins of the TFP401? 

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 90 points

    Hi,

    I have a version of my interface card which doesn't have the buffers fitted and just passes the data through to the daughterboard that has the TFP410 connected to it. 

    Disconnecting the daughter board, so in effect, the TFP401 is transmitting into a open circuit run of about 12cm in length. I am seeing the same sort of distortion at the end of this run as I was previously. Oddly enough, the ODCK pulse actually looked better at the end of the run than it did at the TFP401.

    It might also be worth noting that between the output of the TFP401 and the input to the TFP410, the signals pass through three pairs of connector (1 pair leaving the customer board into a cable harness, 1 pair entering the buffer card from the harness and a final pair from the buffer card to the TFP410 daughter board). How much effect would this have on signal quality?

    Cheers

    Phil

  • 0 in reply to Philip Hale
    TI__Mastermind 35130 points

    Hi Phil,

    The impedance discontinuities from the multiple connectors would cause reflections and have a negative effect on the signal quality. This coupled with the additional trace length is certain to cause issues. 

    To rule it out, what are the trace lengths on the DVI side? Do you see the same behavior at higher frequencies if you probe the inputs?

    Regards,

    I.K.