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DP83822IF: ESD Pulse stops packet flow.

MAHESH R
Prodigy 110 points
Part Number: DP83822IF
Other Parts Discussed in Thread: AM3358, DP83822I, STRIKE

Hi,

We are using DP83822i PHY in our design with AM3358. When we do ESD test, packet flow stops immediately, and it did not recover until cable (fiber) disconnect and connect.

At the time of packet flow stops, we have verified the BMSR register value, it shows link status is up. (BMSR -> 0x784d)

when ESD pulse applied, link status goes down and comes up within a few milliseconds. But packet flow is not happening until cable disconnect and connect.

why packet flow is not happening in this scenario? How cable disconnect & connect brings PHY into a working state?

SDK:
ti-processor-sdk-linux-am335x-evm-06.01.00.08-Linux-x86-Install.bin

PHY: 83822IFRHBR

Thanks,

Mahesh R

  • 0
    TI__Genius 16030 points

    Hello Mahesh,

    Do you have a SFP on the board? If yes, can you do ESD in a way to isolate whether the packet flow issue after ESD is because of PHY or SFP?

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    Intellectual 280 points

    Hi Vikram,
    We have tried some experiments to try and isolate the SFP or PHY, but they are not conclusive.
    We have dumped the register set before and after ESD and don't see any differences (except for errors that occurred during the ESD).
    A Digital Restart (0x001F.14) does not fix the issue.
    Of course a Software Reset (0x001F.15) does fix the issue.
    Also, unplugging and plugging back the Fibre cable fixes the issue.
    We were wondering if you might be able to shed some light on what exactly happens between the SFP and PHY when the cable is removed and inserted.  Hoping that will help us isolate is the issue is with the PHY or the SFP.

    Thanks
    RD

  • 0 in reply to RD
    TI__Genius 16030 points

    Hello RD,

    I was checking for the possible scenarios for this issue, but did not get a clear answer.We will need following to investigate it further :

    - Kindly share the register dump before and after ESD strike.

    - Is LED_1 connected to SFP?

    - When packet flow stops after ESD, do you have link indication?

    - Is the ESD level under test more than what is specified in PHY?

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    Prodigy 110 points

    Hi Vikram,

    1. Register dump,

    Before ESD,

    [ 213.407349] get: 0 == 2100
    [ 213.687068] get: 1 == 784d
    [ 213.747040] get: 2 == 2000
    [ 213.806979] get: 3 == a240
    [ 213.867057] get: 4 == 181
    [ 213.927237] get: 5 == 0
    [ 213.957147] get: 6 == 4
    [ 214.077089] get: 7 == 2001
    [ 214.117301] get: 8 == 0
    [ 214.137282] get: 9 == 20
    [ 214.197027] get: a == 4100
    [ 214.257124] get: b == 1000
    [ 214.317110] get: c == 0
    [ 214.377035] get: d == 401f
    [ 214.437027] get: e == 440
    [ 214.496960] get: f == 0
    [ 214.556948] get: 10 == 205
    [ 214.597098] get: 11 == 108
    [ 214.657102] get: 12 == 8000
    [ 214.717032] get: 13 == 0
    [ 214.777215] get: 14 == 0
    [ 214.837805] get: 15 == 0
    [ 214.897675] get: 16 == 100
    [ 214.957167] get: 17 == 49
    [ 215.017133] get: 18 == 400
    [ 215.077288] get: 19 == 8001
    [ 215.137361] get: 1a == 0
    [ 215.197109] get: 1b == 7d
    [ 215.257094] get: 1c == 5ee
    [ 215.317179] get: 1d == 0
    [ 215.377085] get: 1e == 2
    [ 215.437871] get: 465 == ff01
    [ 215.497741] get: 460 == 551
    [ 215.557745] get: 467 == b03
    [ 215.617820] get: 468 == 4
    [ 215.677738] get: 469 == 440

    Interface went down on ESD pulse,

    [ 403.213561] dp83822: eth1

    [ 403.217247] 0 == 2100
    [ 403.219859] 1 == 7849
    [ 403.222461] 2 == 2000
    [ 403.225062] 3 == a240
    [ 403.228189] 4 == 181
    [ 403.230714] 5 == 0
    [ 403.233054] 6 == 4
    [ 403.235394] 7 == 2001
    [ 403.238472] 8 == 0
    [ 403.240820] 9 == 20
    [ 403.243249] a == 4100
    [ 403.245850] b == 1000
    [ 403.248835] c == 0
    [ 403.251184] d == 401f
    [ 403.253788] e == 440
    [ 403.256538] f == 0
    [ 403.259126] 10 == 204
    [ 403.261737] 11 == 108
    [ 403.264338] 12 == a000
    [ 403.267492] 13 == 0
    [ 403.269928] 14 == 0
    [ 403.272355] 15 == 0
    [ 403.274782] 16 == 100
    [ 403.277769] 17 == 49
    [ 403.280288] 18 == 400
    [ 403.282889] 19 == 8001
    [ 403.285579] 1a == 0
    [ 403.288351] 1b == 7d
    [ 403.290871] 1c == 5ee
    [ 403.293472] 1d == 0
    [ 403.295899] 1e == 2
    [ 403.299317] 0x0465 == ff01
    [ 403.303034] 0x0460 == 551
    [ 403.306917] 0x0467 == b03
    [ 403.310550] 0x0468 == 4
    [ 403.314002] 0x0469 == 440

    Interface came up with in few milli sec,

    [ 404.333619] dp83822: eth1
    [ 404.337307] 0 == 2100
    [ 404.339922] 1 == 784d
    [ 404.342527] 2 == 2000
    [ 404.345127] 3 == a240
    [ 404.348621] 4 == 181
    [ 404.351145] 5 == 0
    [ 404.353488] 6 == 4
    [ 404.355828] 7 == 2001
    [ 404.358933] 8 == 0
    [ 404.361284] 9 == 20
    [ 404.363871] a == 4100
    [ 404.366856] b == 1000
    [ 404.369470] c == 0
    [ 404.371811] d == 401f
    [ 404.374412] e == 440
    [ 404.377292] f == 0
    [ 404.379642] 10 == 205
    [ 404.382245] 11 == 108
    [ 404.384847] 12 == a000
    [ 404.387967] 13 == 0
    [ 404.390404] 14 == 0
    [ 404.392832] 15 == 0
    [ 404.395502] 16 == 100
    [ 404.398595] 17 == 49
    [ 404.401122] 18 == 400
    [ 404.403726] 19 == 8001
    [ 404.406709] 1a == 0
    [ 404.409142] 1b == 7d
    [ 404.411658] 1c == 5ee
    [ 404.414259] 1d == 0
    [ 404.417085] 1e == 2
    [ 404.420200] 0x0465 == ff01
    [ 404.423914] 0x0460 == 551
    [ 404.427822] 0x0467 == b03
    [ 404.431452] 0x0468 == 4
    [ 404.434903] 0x0469 == 440

    2. LED_1 is connected to LOS pin on SFP.

    3. Yes. BMSR register (Bit 2) link status bit shows up.

    4. 4KV and higher causes it to fail. 

    Thanks,

    Mahesh R

  • 0 in reply to MAHESH R
    TI__Genius 16030 points

    Hello Mahesh,

    Team is still looking into possible failure scenario and should be able to indicate to you in a day or two if we could come up with a possible hypothesis. Here are a few follow up queries :

    1. Do you see any dip in 3.3V supply during ESD test? Is it still with-in functional range?

    2. This 4KV is contact discharge as per IEC 61000-4-2?

    3. Can we try following PHY level test to further isolate the problem:

       - Disconnect the cable and after power up put the PHY in analog loopback reg<0x0016>[4:0] = 01000

      - Read register 0x0001. Bit[2] should become 1 (internal link = valid).

      - Now do ESD test and read this register again after the test

    Thanks for your patience. Hopefully we will be able to close on this very soon now.

    --

    Regards,

    Vikram