horizontal sync problem

Lo2

Expert 1935 points

Part Number: SN65DSI84
Other Parts Discussed in Thread: DSI-TUNER

Hello,

we managed to configure the SN65DSI84 almost completely only the horizontal sync is slightly off:

(the last lines from the house icon on the left appear on the right side)

It's a single channel LVDS display, 1280x800, pixel clock 71MHz. The horizontal sync width is 32 px, the backporch is 80 px, the horziontal period is 1440.

On the MIPI side (4 lanes, 213MHz) we use event mode, all other modes (burst, pulse) don't sync correctly (video output staggered, color issues).

Does the DSI have a proper line buffer? Shouldn't burst and event modes work too?

Can we modify/adjust the horizontal timing in the DSI84 when it's not in test pattern generation mode?

Best regards,

Lo2

0x0A 0x05   /* lvds range 71 MHz - lvds pixel clock from mipi A */
0x0B 0x18   /* refclk divider */
0x10 0x26   /* input = 4 lanes */

0x11 0x00
0x12 0x38   /* expected input clock */
0x13 0x00
0x18 0x78   /* polarities / 24BPP mode */

0x19 0x00
0x1A 0x03
0x1B 0x00
/* timings */
0x20 0x00   /* active pixels */
0x21 0x05
0x22 0x00
0x23 0x00
0x24 0x20   /* active lines - only test patterns */
0x25 0x03
0x26 0x00
0x27 0x00
0x28 0x21   /* sync delay */
0x29 0x00
0x2A 0x00
0x2B 0x00
0x2C 0x20   /* hori sync pulse width */
0x2D 0x00
0x2E 0x00
0x2F 0x00
0x30 0x06   /* verti sync pulse width */
0x31 0x00
0x32 0x00
0x33 0x00
0x34 0x50   /* hori back porch */
0x35 0x00
0x36 0x0E   /* verti back porch - only test patterns */
0x37 0x00
0x38 0x30   /* hori front porch - only test patterns */
0x39 0x00
0x3A 0x03   /* verti front porch - only test patterns */
0x3B 0x00
0x3C 0x00
/* 0x3C 0x10 */ /* test screen */
0x3D 0x00
0x3E 0x00

over 3 years ago

0 Ikechukwu Anyiam over 3 years ago

TI__Mastermind 35130 points

Hi Lothar,

Please reference this video to correctly configure the device using the DSI-Tuner: https://training.ti.com/configuring-sn65dsi8x-single-channel-dsi-single-link-lvds-operation

Also reference #2 - 4 in this FAQ: https://e2e.ti.com/support/interface/f/138/t/852871

DSI output from the DSI source must match the settings programmed into the DSI83.

Regards,

I.K.

0 Lo2 over 3 years ago in reply to Ikechukwu Anyiam

Expert 1935 points

Hello I.K.

thanks for your fast reply.

We configured the DSI84 using the DSI-tuner already.

We encountered one issue with this tool: the MIPI sync mode drop down box does not seem to affect the generated output, at least not for the DSI84. We assume this is the correct behavior.

Meanwhile we solved the issue ourself, apparently there is an internal bandwidth or timing restriction inside the DSI84. When we use the settings generated by the DSI84 tuner, the first pixels of each line are apparently the last pictured from the previous active (buffered) line.

We had to increase our MIPI clock to a frequency above the calculated value and had to enable burst mode on the sending side to ensure all active pixels of each line are transmitted in time.

This is probably due to the internal workings of the DSI84.

Best regards,

Lo2

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horizontal sync problem