DP83822HF: Not able to establish link with media converter in FX mode using GLC-FE-100FX-RGD SFP fiber transceiver

Hi,

I found following note in the datasheet :

"TI recommends connecting Signal Detect pin from the Optical Transceiver to the LED_1
pin and enable it using SD_EN bootstrap pin in 100BASE-FX mode. The LED_1 pin is not
used in design and that, if the electrical link between the fiber module and the DP83822 is
broken, disconnected or otherwise disrupted, the link will recover only by initiating a soft
reset through MDIO/MDC interface."

Is it already implemented?

Reg[xA][14]=1 will make 100Base-Fx enable. Is this how it was enabled?

There is a "fiber network circuit" diagram in datasheet showing how fiber connection/components attached should be. Is there any deviation from that diagram in your implementation?

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Regards,

Vikram

Hi Vikram, 

Thanks for your reply.  Answering your questions:

1.  Yes, LED_1 is connected to SFP LOS signal as per the data sheet. 

2. Yes, 100BASE-FX is enabled via register 0x000A bit 14

3. Yes, the SFP module is connected to the PHY as per the diagram on PHY datasheet page 93.  However, the datasheet for the SFP module says this:

RD-/+: These are the differential receiver outputs. They are AC coupled 100Ω differential lines which should be terminated with 100Ω
(differential) at the user SERDES. The AC coupling is done inside the module and is thus not required the host board. The voltage swing
on these lines will be between 400 and 2000 mV differential (200 –1000 mV single ended) when properly terminated.

TD-/+: TD-/+: These are the differential transmitter inputs. They are AC-coupled, differential lines with 100Ωdifferential termination
inside the module.The AC coupling is done inside the module and is thus not required on the host board. The inputs will accept
differential swings of 400–2000mV (200–1000mV single- ended).

So, I have tried the PHY datasheet recommendation as well as direct connections with zero success.

Also, probably important is that access to strapping pins on the PHY is difficult do to the PCB layout so as much as possible I have tried to change PHY behavior using PHY register values rather than strapping options.

Hello,

Just to be sured that PHY is powered up fine and ready to link-up, we can try following after removing SFP module :

1. Analog loopback : reg<0x0016>[4:0]=01000 and check the link-status on BMSR register (reg<0x0001>[2]).

2. Digital loopback : reg<0x006>[4:0] = 00100 and check the link-status on BMSR register (reg<0x0001>[2]).

3. Does writting soft reset recovers the link? : reg<0x001F> = 0x4000

4. Does writting hard reset (reg<0x001F>=0x8000) followed by 100BaseFx enabling recovers the link?

5. Is media converter in the required configuration? Have you tried linking up 2 822s over fiber?

6. Have you tried any other SFP?

7. Is there a pull down connected to TX_Disable pin of SFP? For some of the SFPs we have seen that lower value of pull down ~ 600ohms helps

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Regards,

Vikram

Thanks for your help.  I have been able to obtain a link.  Problem was using the wrong SFP module.  The one I was using couldn't work with a gigabit media converter.  

Now there is another issue that you could maybe comment on.  

After resetting the PHY I sometimes see no Tx and Rx clocks going back to the MAC.  

I suspect that this may be caused by a strapping issue. Maybe something in the MDIO interface not being controlled during PHY reset release??

Any thoughts?

Hello Joel,

Can you read register 0x0467 and see if correct MAC mode is getting selected during faulty reset?